• 1316 引文
  • 19 h-指數
1990 …2020
如果您對這些純文本內容做了任何改變,很快就會看到。

個人檔案

學歷

  • 1991 美國南加州大學電機博士 Ph.D., Univ. of Southern California, U.S.A.

研究專長

  • 超大型積體電路設計與測試 VLSI Design and Testing
  • 超大型積體電路電腦輔助設計 VLSI Computer-Aided Design
  • 計算機演算法 Computer Algorithms
  • 超大型積體電路易測性設計與內建式自我測試VLSI Testable Design and Built-in Self Test

經歷

  • 1997-present 國立成功大學電機系教授
  • 1991 ~ 1997 國立成功大學電機系副教授
  • 2003/8~2004/1 美國史丹福大學訪問教授

指紋 查看啟用 Kuen-Jong Lee 的研究主題。這些主題標籤來自此人的作品。共同形成了獨特的指紋。

  • 16 類似的檔案
Networks (circuits) Engineering & Materials Science
Built-in self test Engineering & Materials Science
Testing Engineering & Materials Science
Clocks Engineering & Materials Science
Data storage equipment Engineering & Materials Science
Shift registers Engineering & Materials Science
Compaction Engineering & Materials Science
Combinatorial circuits Engineering & Materials Science

網絡 國家層面的近期外部合作。點選圓點深入探索詳細資料。

研究計畫 1995 2020

研究成果 1990 2019

Automatic test pattern generation
Compaction
Networks (circuits)
Trimming
Fault detection

A novel test generation method for small-delay defects with user-defined fault model

Shang, C. J., Wu, C. H., Lee, K-J. & Chen, Y. H., 2019 四月 1, 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019. Institute of Electrical and Electronics Engineers Inc., 8741773. (2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019).

研究成果: Conference contribution

Defects
defects
stems
time measurement
Networks (circuits)

Generating Compact Test Patterns for DC and AC Faults Using One ATPG Run

Kung, Y. C., Lee, K-J. & Reddy, S. M., 2019 一月 23, International Test Conference 2018, ITC 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 8624678. (Proceedings - International Test Conference; 卷 2018-October).

研究成果: Conference contribution

Fault
Networks (circuits)
Experiments
Count
Coverage
1 引文 (Scopus)
Built-in self test
Failure analysis
Clocks
Controllers
Networks (circuits)

論文

3D-IC Built-In Diagnosis Architecture for TSVs with Different Placement and Impact Ranges of Crosstalk Faults

作者: 文軒, 許., 2016 二月 16

監督員: Lee, K. (Supervisor)

學生論文: Master's Thesis

A High-Efficiency Hybrid Multicast Routing Approach for Mesh-Based Networks-on-Chip

作者: 俊緯, 吳., 2018 二月 5

監督員: Lee, K. (Supervisor)

學生論文: Master's Thesis

A Low Area Overhead BIST Architecture Based on Response Feedback and Logic Reseeding

作者: 崇閔, 蕭., 2014 八月 11

監督員: Lee, K. (Supervisor)

學生論文: Master's Thesis

A Novel Test Generation Method for Small-Delay Defects with User-defined Fault Model

作者: 朝鈞, 商., 2019

監督員: Lee, K. (Supervisor)

學生論文: Master's Thesis

A Run-Pause-Resume Silicon Debug Technique with Cycle-Granularity for Multiple Clock Domain Systems

作者: 碩聯, 洪., 2017 八月 31

監督員: Lee, K. (Supervisor)

學生論文: Master's Thesis