• 1348 引文
  • 19 h-指數
1990 …2020
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研究成果 1990 2019

2019
Automatic test pattern generation
Compaction
Networks (circuits)
Trimming
Fault detection

A novel test generation method for small-delay defects with user-defined fault model

Shang, C. J., Wu, C. H., Lee, K-J. & Chen, Y. H., 2019 四月 1, 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019. Institute of Electrical and Electronics Engineers Inc., 8741773. (2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019).

研究成果: Conference contribution

Defects
defects
stems
time measurement
Networks (circuits)

Generating Compact Test Patterns for DC and AC Faults Using One ATPG Run

Kung, Y. C., Lee, K. J. & Reddy, S. M., 2019 一月 23, International Test Conference 2018, ITC 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 8624678. (Proceedings - International Test Conference; 卷 2018-October).

研究成果: Conference contribution

Fault
Networks (circuits)
Experiments
Count
Coverage
1 引文 (Scopus)
Built-in self test
Failure analysis
Clocks
Controllers
Networks (circuits)

Time-related hardware trojan attacks on processor cores

Kuo, M. H., Hu, C. M. & Lee, K. J., 2019 九月, Proceedings - 2019 IEEE International Test Conference in Asia, ITC-Asia 2019. Institute of Electrical and Electronics Engineers Inc., p. 43-48 6 p. 8872047. (Proceedings - 2019 IEEE International Test Conference in Asia, ITC-Asia 2019).

研究成果: Conference contribution

attack
central processing units
Clocks
Time delay
hardware
2018

A Dynamic-Key Secure Scan Structure Against Scan-Based Side Channel and Memory Cold Boot Attacks

Wu, C. C., Kuo, M. H. & Lee, K-J., 2018 十二月 6, Proceedings - 2018 IEEE 27th Asian Test Symposium, ATS 2018. IEEE Computer Society, p. 48-53 6 p. 8567409. (Proceedings of the Asian Test Symposium; 卷 2018-October).

研究成果: Conference contribution

Data storage equipment
Networks (circuits)
Observability
Controllability
3 引文 (Scopus)

A Hybrid Multicast Routing Approach with Enhanced Methods for Mesh-Based Networks-on-Chip

Wu, C. W., Lee, K. J. & Su, A. P., 2018 九月 1, 於 : IEEE Transactions on Computers. 67, 9, p. 1231-1245 15 p., 8309347.

研究成果: Article

Multicast Routing
Routing algorithms
Deadlock
Routing Algorithm
Mesh

A Repair-for-Diagnosis Methodology for Logic Circuits

Wu, C. H., Lin, S. L., Lee, K-J. & Reddy, S. M., 2018 十一月 1, 於 : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 26, 11, p. 2254-2267 14 p., 8423443.

研究成果: Article

Logic circuits
Repair
Defects
Networks (circuits)
Failure analysis
2 引文 (Scopus)

Generating compact test patterns for stuck-at faults and transition faults in one ATPG run

Kung, Y. C., Lee, K. J. & Reddy, S. M., 2018 九月 11, Proceedings - 2nd IEEE International Test Conference in Asia, ITC-Asia 2018. Institute of Electrical and Electronics Engineers Inc., p. 1-6 6 p. 8462939. (Proceedings - 2nd IEEE International Test Conference in Asia, ITC-Asia 2018).

研究成果: Conference contribution

Networks (circuits)

Test compression with single-input data spreader and multiple test sessions

Chen, C. W., Kong, Y. C. & Lee, K-J., 2018 一月 24, Proceedings - 2017 IEEE 26th Asian Test Symposium, ATS 2017. IEEE Computer Society, p. 24-29 6 p. (Proceedings of the Asian Test Symposium).

研究成果: Conference contribution

Spreaders
Program processors
Networks (circuits)
Data compression
Integrated circuits
2017

A low power synthesis flow for multi-rate systems

Kuo, H. P., Su, A. P. & Lee, K-J., 2017 六月 5, 2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017. Institute of Electrical and Electronics Engineers Inc., 7939677

研究成果: Conference contribution

Clocks
Synchronization
Electric power utilization
Scheduling
Throughput
1 引文 (Scopus)

A Run-Pause-Resume silicon debug technique for multiple clock domain systems

Hong, S. L. & Lee, K. J., 2017 十一月 3, ITC-Asia 2017 - International Test Conference in Asia. Institute of Electrical and Electronics Engineers Inc., p. 46-51 6 p. 8097109. (ITC-Asia 2017 - International Test Conference in Asia).

研究成果: Conference contribution

Clocks
Silicon
Flip flop circuits
Networks (circuits)
Hardware

A run-pause-resume silicon debug technique with cycle granularity for multiple clock domain systems

Hong, S. L. & Lee, K-J., 2017 十二月 29, Proceedings - 2017 IEEE International Test Conference, ITC 2017. Institute of Electrical and Electronics Engineers Inc., p. 1-10 10 p. (Proceedings - International Test Conference; 卷 2017-December).

研究成果: Conference contribution

Granularity
Clocks
Silicon
Cycle
Methodology
2 引文 (Scopus)
Crosstalk
Topology
Silicon
Testing

Foreword

Wu, C. W., Lee, K. J., Wang, L. C. & Huang, S. Y., 2017 十一月 3, 於 : ITC-Asia 2017 - International Test Conference in Asia. p. iv 8097094.

研究成果: Editorial

Test generation for open and delay faults in CMOS circuits

Wu, C. H., Lee, K. J. & Reddy, S. M., 2017 十一月 3, ITC-Asia 2017 - International Test Conference in Asia. Institute of Electrical and Electronics Engineers Inc., p. 21-26 6 p. 8097104. (ITC-Asia 2017 - International Test Conference in Asia).

研究成果: Conference contribution

Networks (circuits)
Dynamic models
Transistors
Wire
9 引文 (Scopus)
Networks (circuits)
Switches
Flip flop circuits
Data reduction
2016
2 引文 (Scopus)

3D-IC test architecture for TSVs with different impact ranges of crosstalk faults

Hsu, W. H., Kochte, M. A. & Lee, K. J., 2016 五月 31, 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016. Institute of Electrical and Electronics Engineers Inc., 7482554. (2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016).

研究成果: Conference contribution

Crosstalk
crosstalk
Silicon
silicon
chips
2 引文 (Scopus)

An on-chip self-Test architecture with test patterns recorded in scan chains

Lee, K. J., Tang, P. H. & Kochte, M. A., 2016 七月 2, Proceedings - 2016 IEEE International Test Conference, ITC 2016. Institute of Electrical and Electronics Engineers Inc., 7805865. (Proceedings - International Test Conference; 卷 0).

研究成果: Conference contribution

Chip
Controllers
Built-in self test
Cell
Architecture
3 引文 (Scopus)

A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling

Lu, L. Y., Chang, C. Y., Chen, Z. H., Yeh, B. T., Lu, T. H., Chen, P. Y., Tang, P. H., Lee, K. J., Chiou, L. Y., Chang, S. J., Tsai, C. H., Chen, C. H. & Lin, J. M., 2016 三月 7, 2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016. Institute of Electrical and Electronics Engineers Inc., p. 17-18 2 p. 7427980. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; 卷 25-28-January-2016).

研究成果: Conference contribution

Program processors
Microprocessor chips
Temperature
Voltage scaling
Dynamic frequency scaling
3 引文 (Scopus)

A Test-per-cycle BIST architecture with low area overhead and no storage requirement

Shiao, C. M., Lien, W. C. & Lee, K-J., 2016 五月 31, 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016. Institute of Electrical and Electronics Engineers Inc., 7482556. (2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016).

研究成果: Conference contribution

Built-in self test
Clocks
requirements
cycles
clocks
1 引文 (Scopus)

Autonomous Testing for 3D-ICs with IEEE Std. 1687

Ye, J. C., Kochte, M. A., Lee, K. J. & Wunderlich, H. J., 2016 十二月 22, Proceedings - 2016 IEEE 25th Asian Test Symposium, ATS 2016. IEEE Computer Society, p. 215-220 6 p. 7796115. (Proceedings of the Asian Test Symposium).

研究成果: Conference contribution

Controllers
Testing
1 引文 (Scopus)

Distinguishing dynamic bridging faults and transition delay faults

Wu, C. H., Lee, S. J. & Lee, K. J., 2016 七月 21, Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015. Ren, J., Tang, T-A., Ye, F. & Yu, H. (編輯). Institute of Electrical and Electronics Engineers Inc., 7516978. (Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015).

研究成果: Conference contribution

Networks (circuits)
Defects
Industry

Output bit selection methodology for test response compaction

Lien, W. C. & Lee, K. J., 2016 七月 2, Proceedings - 2016 IEEE International Test Conference, ITC 2016. Institute of Electrical and Electronics Engineers Inc., 7805873. (Proceedings - International Test Conference; 卷 0).

研究成果: Conference contribution

Compaction
Methodology
Output
Networks (circuits)
Product design
1 引文 (Scopus)

Repairable Cell-Based Chip Design for Simultaneous Yield Enhancement and Fault Diagnosis

Lin, S. L., Wu, C. H. & Lee, K. J., 2016 十二月 22, Proceedings - 2016 IEEE 25th Asian Test Symposium, ATS 2016. IEEE Computer Society, p. 25-30 6 p. 7796076. (Proceedings of the Asian Test Symposium).

研究成果: Conference contribution

Failure analysis
Repair
Defects
Networks (circuits)
4 引文 (Scopus)

Test and diagnosis pattern generation for dynamic bridging faults and transition delay faults

Wu, C. H., Lee, S. J. & Lee, K. J., 2016 三月 7, 2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016. Institute of Electrical and Electronics Engineers Inc., p. 755-760 6 p. 7428102. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; 卷 25-28-January-2016).

研究成果: Conference contribution

Networks (circuits)
Compaction
Defects
7 引文 (Scopus)

Transformation of multiple fault models to a unified model for ATPG efficiency enhancement

Wu, C. H. & Lee, K. J., 2016 七月 2, Proceedings - 2016 IEEE International Test Conference, ITC 2016. Institute of Electrical and Electronics Engineers Inc., 7805866. (Proceedings - International Test Conference; 卷 0).

研究成果: Conference contribution

Fault
Enhancement
Model
Transform faults
Test Generation
2015
3 引文 (Scopus)

A breakpoint-based silicon debug technique with cycle-granularity for handshake-based SoC

Chen, H. C., Wu, C. R., Li, K. S. M. & Lee, K. J., 2015 四月 22, Proceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015. Institute of Electrical and Electronics Engineers Inc., p. 1281-1284 4 p. 7092589. (Proceedings -Design, Automation and Test in Europe, DATE; 卷 2015-April).

研究成果: Conference contribution

Silicon
Networks (circuits)
Granulation
System-on-chip

A high-performance SoC debug platform

Liu, K. K., Hsu, W. H. & Lee, K. J., 2015 一月 1, 於 : Smart Science. 3, 4, p. 202-208 7 p.

研究成果: Article

High Performance
Debugging
Design Automation
Automation
Trigger
6 引文 (Scopus)

An efficient 3D-IC on-chip test framework to embed TSV testing in memory BIST

Li, L. C., Hsu, W. H., Lee, K. J. & Hsu, C. L., 2015 三月 11, 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015. Institute of Electrical and Electronics Engineers Inc., p. 520-525 6 p. 7059059. (20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015).

研究成果: Conference contribution

Built-in self test
Chip
Data storage equipment
Testing
Integrated circuits
2 引文 (Scopus)

An efficient diagnosis-aware pattern generation procedure for transition faults

Lee, K. J. & Wu, C. H., 2015 二月 6, Proceedings - 2014 IEEE International Test Conference, ITC 2014. Institute of Electrical and Electronics Engineers Inc., 7035361. (Proceedings - International Test Conference; 卷 2015-February).

研究成果: Conference contribution

Fault
Networks (circuits)
Failure analysis
Program processors
Compaction
4 引文 (Scopus)

Improve transition fault diagnosability via observation point insertion

Wu, C. H., Wang, Y. D. & Lee, K-J., 2015 五月 28, 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015. Institute of Electrical and Electronics Engineers Inc., 7114571. (2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015).

研究成果: Conference contribution

Networks (circuits)
2014
8 引文 (Scopus)

An efficient diagnosis method to deal with multiple fault-pairs simultaneously using a single circuit model

Wu, C. H., Lee, K-J. & Lien, W. C., 2014 一月 1, Proceedings - 2014 IEEE 32nd VLSI Test Symposium, VTS 2014. IEEE Computer Society, 6818790. (Proceedings of the IEEE VLSI Test Symposium).

研究成果: Conference contribution

Networks (circuits)
Data structures
6 引文 (Scopus)

An efficient diagnosis pattern generation procedure to distinguish stuck-at faults and bridging faults

Wu, C. H. & Lee, K. J., 2014 十二月 7, Proceedings - 23rd Asian Test Symposium, ATS 2014. IEEE Computer Society, p. 306-311 6 p. 06979118. (Proceedings of the Asian Test Symposium).

研究成果: Conference contribution

Defects
Networks (circuits)
Failure analysis
Program processors
Integrated circuits
23 引文 (Scopus)
Testing
Refining
Networks (circuits)
4 引文 (Scopus)

Efficient LFSR Reseeding Based on Internal-Response Feedback

Lien, W. C., Lee, K-J., Hsieh, T. Y. & Chakrabarty, K., 2014 十二月 3, 於 : Journal of Electronic Testing: Theory and Applications (JETTA). 30, 6, p. 673-685 13 p.

研究成果: Article

Feedback
Seed
Networks (circuits)
Built-in self test
Integrated circuits
1 引文 (Scopus)

Efficient pattern generation for transition-fault diagnosis using combinational circuit model

Wang, Y. D. & Lee, K-J., 2014 一月 23, Proceedings - 2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014. Zhou, J. & Tang, T-A. (編輯). Institute of Electrical and Electronics Engineers Inc., 7021499. (Proceedings - 2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014).

研究成果: Conference contribution

Combinatorial circuits
Failure analysis
Networks (circuits)

MULTI-POINT TEMPERATURE SENSING METHOD FOR INTEGRATED CIRCUIT CHIP AND SYSTEM OF THE SAME

貢獻的翻譯標題: 適用於積體電路晶片之多點溫度感測方法及其系統Lee, K-J., Chen, C-H., Su, W-Y., Chang, S-J., Chiou, L-Y., Kuo, C-H., Tsai, C-H. & Lin, J-M., 2014 十一月 20, 專利號 9448122

研究成果: Patent

Temperature sensors
Integrated circuits
Temperature
Temperature control
Control systems
3 引文 (Scopus)
Network protocols
Interfaces (computer)
Communication
3 引文 (Scopus)

Output-bit selection with X-avoidance using multiple counters for test-response compaction

Lien, W. C., Lee, K-J., Chakrabarty, K. & Hsieh, T. Y., 2014 一月 1, Proceedings - 2014 19th IEEE European Test Symposium, ETS 2014. IEEE Computer Society, 6847823. (Proceedings - 2014 19th IEEE European Test Symposium, ETS 2014).

研究成果: Conference contribution

Compaction
Networks (circuits)
Experiments
2 引文 (Scopus)

Output selection for test response compaction based on multiple counters

Lien, W. C., Lee, K-J., Chakrabarty, K. & Hsieh, T. Y., 2014 一月 1, Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014. IEEE Computer Society, 6834865. (Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014).

研究成果: Conference contribution

Compaction
2013
5 引文 (Scopus)

An efficient deadlock-free multicast routing algorithm for mesh-based networks-on-chip

Lee, K. J., Chang, C. Y. & Yang, H. Y., 2013 八月 15, 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013. 6533824. (2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013).

研究成果: Conference contribution

Routing algorithms
Routers
Network-on-chip
Communication
10 引文 (Scopus)
Seed
Networks (circuits)
Inventory control
Data storage equipment
2 引文 (Scopus)

A new LFSR reseeding scheme via internal response feedback

Lien, W. C., Lee, K-J., Hsieh, T. Y. & Chakrabarty, K., 2013 一月 1, 於 : Proceedings of the Asian Test Symposium. p. 97-102 6 p., 6690622.

研究成果: Conference article

Seed
Feedback
Built-in self test
Networks (circuits)
Integrated circuits
6 引文 (Scopus)

Counter-based output selection for test response compaction

Lien, W. C., Lee, K-J., Hsieh, T. Y., Chakrabarty, K. & Wu, Y. H., 2013 一月 7, 於 : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 32, 1, p. 152-164 13 p., 6387700.

研究成果: Article

Compaction
Hardware
Networks (circuits)
2012
1 引文 (Scopus)

Accumulator-based output selection for test response compaction

Lien, W. C., Lee, K-J., Hsieh, T. Y., Chien, S. S. & Chakrabarty, K., 2012 九月 28, p. 2313-2316. 4 p.

研究成果: Paper

Compaction
Networks (circuits)
12 引文 (Scopus)

A test-per-clock LFSR reseeding algorithm for concurrent reduction on test sequence length and test data volume

Lien, W. C., Lee, K-J. & Hsieh, T. Y., 2012 十二月 1, Proceedings - 2012 IEEE 21st Asian Test Symposium, ATS 2012. p. 278-283 6 p. 6394216. (Proceedings of the Asian Test Symposium).

研究成果: Conference contribution

Seed
Clocks
Built-in self test
9 引文 (Scopus)
Networks (circuits)
Automatic test pattern generation
Testing
1 引文 (Scopus)

Output bit selection for test response compaction based on a single counter

Lee, K-J., Lien, W. C. & Hsieh, T. Y., 2012 十二月 1, ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings. 6467671. (ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings).

研究成果: Conference contribution

Compaction
Hardware
Networks (circuits)