李 昆忠

研究成果

每年研究成果 1990 1995 1998 1999 2000 2001 2002 2004 2005 2006 2007 2008 2009 2011 2012 2014 2015 2016 2017 2018 2019 2022 2023

• 85 Conference contribution
• 61 Article
• 20 Conference article
• 6 Editorial
• 13 更多
  • 6 Patent
  • 5 Paper
  • 2 Chapter

每年研究成果

每年研究成果

搜尋結果

• 2022

  A Dynamic-Key Based Secure Scan Architecture for Manufacturing and In-Field IC Testing

  Lee, K. J., Liu, C. A. & Wu, C. C., 2022, 於: IEEE Transactions on Emerging Topics in Computing. 10, 1, p. 373-385 13 p.

  研究成果: Article › 同行評審

  • Data storage equipment 100%
  • Testing 84%
  • Hardware security 84%
  • Design for testability 45%
  • Networks (circuits) 36%
  7 引文 斯高帕斯（Scopus）

• An Efficient Procedure to Generate Highly Compact Diagnosis Patterns for Transition Faults

  Lee, K. J., Wu, C. H. & Hou, T. Y., 2022 3月 1, 於: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 41, 3, p. 737-749 13 p.

  研究成果: Article › 同行評審

  • Networks (circuits) 100%
  2 引文 斯高帕斯（Scopus）

• A Secure JTAG Wrapper for SoC Testing and Debugging

  Lee, K. J., Lu, Z. Y. & Yeh, S. C., 2022, 於: IEEE Access. 10, p. 37603-37612 10 p.

  研究成果: Article › 同行評審

  開啟存取

  • System-on-chip 100%
  • Authentication 56%
  • Program processors 55%
  • Testing 50%
  • Hardware security 41%
  2 引文 斯高帕斯（Scopus）

• Efficient Test Compression Configuration Selection

  Ye, C. S., Zheng, S. X., Tsai, F. J., Wang, C., Lee, K. J., Cheng, W. T., Reddy, S. M., Zawada, J., Kassab, M. & Rajski, J., 2022 7月 1, 於: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 41, 7, p. 2323-2336 14 p.

  研究成果: Article › 同行評審

  • Computer hardware 100%
  • System-on-chip 86%
  • Product design 84%
  • Costs 65%
  2 引文 斯高帕斯（Scopus）

• Using both Stable and Unstable SRAM Bits for the Physical Unclonable Function

  Lai, Z. W., Huang, P. H. & Lee, K. J., 2022 10月, 於: Journal of Electronic Testing: Theory and Applications (JETTA). 38, 5, p. 511-525 15 p.

  研究成果: Article › 同行評審

  • Hardware security 100%
  • Static random access storage 87%
  • Focused ion beams 10%
  • Photons 9%
  • Authentication 6%
• 2021

  Test Chips with Scan-Based Logic Arrays

  Chen, Y. H., Hsu, C. M. & Lee, K. J., 2021 4月, 於: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 40, 4, p. 790-802 13 p., 9144517.

  研究成果: Article › 同行評審

  • Defects 100%
  5 引文 斯高帕斯（Scopus）
• 2020

  Generating Single-and Double-Pattern Tests for Multiple CMOS Fault Models in One ATPG Run

  Kung, Y. C., Lee, K. J. & Reddy, S. M., 2020 6月, 於: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 39, 6, p. 1340-1345 6 p., 8732359.

  研究成果: Article › 同行評審

  • Networks (circuits) 100%
  • Transistors 77%
  10 引文 斯高帕斯（Scopus）
• 2019

  An Efficient Diagnosis-Aware ATPG Procedure to Enhance Diagnosis Resolution and Test Compaction

  Wu, C. H., Lee, K. J. & Reddy, S. M., 2019 9月, 於: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 27, 9, p. 2105-2118 14 p., 8742768.

  研究成果: Article › 同行評審

  • Automatic test pattern generation 100%
  • Compaction 55%
  • Networks (circuits) 15%
  • Trimming 11%
  • Fault detection 8%
  13 引文 斯高帕斯（Scopus）

• On-Chip Self-Test Methodology With All Deterministic Compressed Test Patterns Recorded in Scan Chains

  Lee, K. J., Chen, B. R. & Kochte, M. A., 2019 2月, 於: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 38, 2, p. 309-321 13 p., 8299475.

  研究成果: Article › 同行評審

  • Built-in self test 100%
  • Failure analysis 69%
  • Clocks 68%
  • Networks (circuits) 44%
  • Controllers 43%
  10 引文 斯高帕斯（Scopus）
• 2018

  A Hybrid Multicast Routing Approach with Enhanced Methods for Mesh-Based Networks-on-Chip

  Wu, C. W., Lee, K. J. & Su, A. P., 2018 9月 1, 於: IEEE Transactions on Computers. 67, 9, p. 1231-1245 15 p., 8309347.

  研究成果: Article › 同行評審

  • Network on chip 100%
  • Multicast Routing 90%
  • Routing algorithms 50%
  • Traffic 41%
  • Mesh 39%
  18 引文 斯高帕斯（Scopus）

• A Repair-for-Diagnosis Methodology for Logic Circuits

  Wu, C. H., Lin, S. L., Lee, K. J. & Reddy, S. M., 2018 11月, 於: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 26, 11, p. 2254-2267 14 p., 8423443.

  研究成果: Article › 同行評審

  • Logic circuits 100%
  • Repair 71%
  • Defects 59%
  • Networks (circuits) 24%
  • Failure analysis 12%
  3 引文 斯高帕斯（Scopus）
• 2017

  Built-In Test and Diagnosis for TSVs with Different Placement Topologies and Crosstalk Impact Ranges

  Hsu, W. H., Kochte, M. A. & Lee, K. J., 2017 6月, 於: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 36, 6, p. 1004-1017 14 p.

  研究成果: Article › 同行評審

  • Crosstalk 100%
  • Silicon 69%
  • Topology 60%
  • Integrated circuit design 13%
  • Testing 11%
  9 引文 斯高帕斯（Scopus）

• Test Stimulus Compression Based on Broadcast Scan with One Single Input

  Chen, J. Z. & Lee, K. J., 2017 1月, 於: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 36, 1, p. 184-197 14 p., 7463526.

  研究成果: Article › 同行評審

  • Networks (circuits) 100%
  • Switches 86%
  • Data reduction 71%
  • Flip flop circuits 70%
  13 引文 斯高帕斯（Scopus）
• 2015

  A high-performance SoC debug platform

  Liu, K. K., Hsu, W. H. & Lee, K. J., 2015 1月 1, 於: Smart Science. 3, 4, p. 202-208 7 p.

  研究成果: Article › 同行評審

  • System-on-chip 100%
  • High Performance 67%
  • Debugging 39%
  • Design Automation 34%
  • Environment 29%

• A High-Performance SoC Debug Platform

  Liu, K. K., Hsu, W. H. & Lee, K. J., 2015, 於: Smart Science. 3, 4, p. 202-208 7 p.

  研究成果: Article › 同行評審

  開啟存取

  • System-on-chip 100%
  • High Performance 67%
  • Debugging 39%
  • Design Automation 34%
  • Environment 29%
• 2014

  Capture-power-safe test pattern determination for at-speed scan-based testing

  Li, Y. H., Lien, W. C., Lin, I. C. & Lee, K. J., 2014 1月, 於: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 33, 1, p. 127-138 12 p., 6685941.

  研究成果: Article › 同行評審

  • Testing 100%
  • Refining 94%
  • Networks (circuits) 53%
  29 引文 斯高帕斯（Scopus）

• Efficient LFSR Reseeding Based on Internal-Response Feedback

  Lien, W. C., Lee, K. J., Hsieh, T. Y. & Chakrabarty, K., 2014 12月 3, 於: Journal of Electronic Testing: Theory and Applications (JETTA). 30, 6, p. 673-685 13 p.

  研究成果: Article › 同行評審

  • Seed 100%
  • Feedback 91%
  • Networks (circuits) 79%
  • Built-in self test 59%
  • Integrated circuits 44%
  7 引文 斯高帕斯（Scopus）

• On deadlock problem of on-chip buses supporting out-of-order transactions

  Chang, C. Y. & Lee, K. J., 2014 3月, 於: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 22, 3, p. 484-496 13 p., 6490417.

  研究成果: Article › 同行評審

  • Network protocols 100%
  • Communication 36%
  3 引文 斯高帕斯（Scopus）
• 2013

  An efficient on-chip test generation scheme based on programmable and multiple twisted-ring counters

  Lien, W. C., Lee, K. J., Hsieh, T. Y. & Ang, W. L., 2013, 於: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 32, 8, p. 1254-1264 11 p., 6559094.

  研究成果: Article › 同行評審

  • Seed 100%
  • Networks (circuits) 79%
  • Inventory control 62%
  • Data storage equipment 29%
  13 引文 斯高帕斯（Scopus）

• Counter-based output selection for test response compaction

  Lien, W. C., Lee, K-J., Hsieh, T. Y., Chakrabarty, K. & Wu, Y. H., 2013 1月 7, 於: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 32, 1, p. 152-164 13 p., 6387700.

  研究成果: Article › 同行評審

  • Compaction 100%
  • Computer hardware 23%
  • Networks (circuits) 21%
  7 引文 斯高帕斯（Scopus）
• 2012

  Efficient overdetection elimination of acceptable faults for yield improvement

  Lee, K. J., Hsieh, T. Y. & Breuer, M. A., 2012 5月, 於: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 31, 5, p. 754-764 11 p., 6186858.

  研究成果: Article › 同行評審

  • Networks (circuits) 100%
  • Automatic test pattern generation 92%
  • Testing 31%
  15 引文 斯高帕斯（Scopus）
• 2011

  An error-tolerance-based test methodology to support product grading for yield enhancement

  Hsieh, T. Y., Lee, K. J. & Breuer, M. A., 2011 6月, 於: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 30, 6, p. 930-934 5 p., 5768131.

  研究成果: Article › 同行評審

  • Networks (circuits) 100%
  7 引文 斯高帕斯（Scopus）

• Effective hybrid test program development for software-based self-testing of pipeline processor cores

  Lu, T. H., Chen, C. H. & Lee, K. J., 2011 3月, 於: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 19, 3, p. 516-520 5 p., 5356222.

  研究成果: Article › 同行評審

  • Pipelines 100%
  • Testing 67%
  • Macros 59%
  • Data storage equipment 39%
  33 引文 斯高帕斯（Scopus）

• Programmable system-on-chip for silicon prototyping

  Huang, C. M., Wu, C. M., Yang, C. C., Chen, S. L., Chen, C. S., Wang, J. J., Lee, K. J. & Wey, C. L., 2011 3月 1, 於: IEEE Transactions on Industrial Electronics. 58, 3, p. 830-838 9 p., 4926187.

  研究成果: Article › 同行評審

  • System-on-chip 100%
  • Silicon 77%
  • Costs 10%
  16 引文 斯高帕斯（Scopus）

• Test response compaction via output bit selection

  Lee, K. J., Lien, W. C. & Hsieh, T. Y., 2011 10月, 於: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 30, 10, p. 1534-1544 11 p., 6022010.

  研究成果: Article › 同行評審

  • Compaction 100%
  • Networks (circuits) 43%
  • Automatic test pattern generation 30%
  • Shift registers 24%
  • Set theory 12%
  18 引文 斯高帕斯（Scopus）
• 2010

  On-chip SOC test platform design based on IEEE 1500 standard

  Lee, K. J., Hsieh, T. Y., Chang, C. Y., Hong, Y. T. & Huang, W. C., 2010 7月, 於: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 18, 7, p. 1134-1139 6 p., 5229351.

  研究成果: Article › 同行評審

  • Built-in self test 100%
  • IEEE Standards 86%
  • System-on-chip 82%
  • Data storage equipment 49%
  • Testing 41%
  11 引文 斯高帕斯（Scopus）
• 2008

  An error rate based test methodology to support error-tolerance

  Hsieh, T. Y., Lee, K. J. & Breuer, M. A., 2008 3月, 於: IEEE Transactions on Reliability. 57, 1, p. 204-214 11 p.

  研究成果: Article › 同行評審

  • Sampling 100%
  • Networks (circuits) 78%
  19 引文 斯高帕斯（Scopus）
• 2007

  A design automation system for SOC test platform

  Huang, W. C., Lee, K. J., Chang, C. Y. & Wu, Y. H., 2007 6月, 於: International Journal of Electrical Engineering. 14, 3, p. 219-227 9 p.

  研究成果: Article › 同行評審

  • Automation 100%
  • Electronic design automation 17%
  • Intellectual property core 15%
  • User interfaces 10%
  • Controllers 6%

• Preventing over-detection of acceptable faults for yield enhancement

  Hsieh, T. Y., Lee, K-J. & Breuer, M. A., 2007 6月, 於: International Journal of Electrical Engineering. 14, 3, p. 185-193 9 p.

  研究成果: Article › 同行評審

  • Degradation 100%
  • Defects 98%
  • Testing 73%
  1 引文 斯高帕斯（Scopus）
• 2003

  A hybrid LFSR design for low power applications

  Huang, T. C. & Lee, K. J., 2003 2月, 於: Journal of the Chinese Institute of Electrical Engineering, Transactions of the Chinese Institute of Engineers, Series E/Chung KuoTien Chi Kung Chieng Hsueh K'an. 10, 1, p. 1-9 9 p.

  研究成果: Article › 同行評審

  • Clocks 100%
  • Demultiplexing 69%
  • Broadcasting 47%
  • Compression testing 32%
  • Shift registers 29%

• Test pattern generation and clock disabling for simultaneous test time and power reduction

  Chen, J. J., Yang, C. K. & Lee, K. J., 2003 3月, 於: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 22, 3, p. 363-369 7 p.

  研究成果: Article › 同行評審

  • Clocks 100%
  • Energy dissipation 66%
  • Networks (circuits) 43%
  • Electric power utilization 28%
  • Testing 20%
  25 引文 斯高帕斯（Scopus）
• 2002

  A 0.5 μm concurrent testable chip of a fifth-order g_m-C filter

  Lee, K. J. & Wang, W. C., 2002 9月, 於: Analog Integrated Circuits and Signal Processing. 32, 3, p. 231-247 17 p.

  研究成果: Article › 同行評審

  • Error 100%
  • Voltage 96%
  • Networks (circuits) 73%
  • Error detection 48%
  • Low pass filters 48%
  3 引文 斯高帕斯（Scopus）

• A current-mode BIST structure of DACs

  Wen, Y. C. & Lee, K. J., 2002 4月, 於: Measurement: Journal of the International Measurement Confederation. 31, 3, p. 147-163 17 p.

  研究成果: Article › 同行評審

  • self tests 100%
  • Built-in self test 73%
  • nonlinearity 33%
  • Electric potential 30%
  • electric potential 24%
  5 引文 斯高帕斯（Scopus）

• An efficient BIST method for distributed small buffers

  Jone, W. B., Huang, D. C., Wu, S. C. & Lee, K. J., 2002 8月, 於: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 10, 4, p. 512-514 3 p.

  研究成果: Article › 同行評審

  • Data storage equipment 100%
  • Testing 84%
  • Computer hardware 32%
  10 引文 斯高帕斯（Scopus）

• An efficient deterministic test pattern generator for scan-based BIST environment

  Wang, W. L. & Lee, K. J., 2002 2月, 於: Journal of Electronic Testing: Theory and Applications (JETTA). 18, 1, p. 43-53 11 p.

  研究成果: Article › 同行評審

  • Shift registers 100%
  • Built-in self test 99%
  • Feedback 50%
  • Logic circuits 13%
  • Clocks 9%

• An interleaving technique for reducing peak power in multiple-chain scan circuits during test application

  Lee, K. J. & Huang, T. C., 2002 12月, 於: Journal of Electronic Testing: Theory and Applications (JETTA). 18, 6, p. 627-636 10 p.

  研究成果: Article › 同行評審

  • Networks (circuits) 100%
  • Testing 46%
  2 引文 斯高帕斯（Scopus）
• 2001

  A hierarchical test control architecture for SOC design

  Lee, K-J. & Huang, C. I., 2001 11月 1, 於: Journal of the Chinese Institute of Electrical Engineering, Transactions of the Chinese Institute of Engineers, Series E/Chung KuoTien Chi Kung Chieng Hsueh K'an. 8, 4, p. 355-363 9 p.

  研究成果: Article › 同行評審

  • Intellectual property core 100%
  • Integrated circuit design 96%
  • IEEE Standards 84%

• A low-power LFSR architecture

  Huang, T. C. & Lee, K. J., 2001, 於: Proceedings of the Asian Test Symposium. p. 470 1 p., 80.

  研究成果: Article › 同行評審

  • Built-in self test 100%
  • Clocks 68%
  • Networks (circuits) 44%
  9 引文 斯高帕斯（Scopus）

• Analysis and generation of control and observation structures for analog circuits

  Wen, Y. C. & Lee, K. J., 2001 1月, 於: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 20, 1, p. 165-171 7 p.

  研究成果: Article › 同行評審

  • Analog circuits 100%
  • Switches 7%

• An on-chip march pattern generator for testing embedded memory cores

  Wang, W. L., Lee, K. J. & Wang, J. F., 2001 10月, 於: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 9, 5, p. 730-735 6 p.

  研究成果: Article › 同行評審

  • Data storage equipment 100%
  • Testing 84%
  • Shift registers 40%
  • Set theory 21%
  • Computer hardware 19%
  16 引文 斯高帕斯（Scopus）

• Fast deterministic test pattern generation for scan-based bist environment

  Wang, W. L. & Lee, K. J., 2001 11月 1, 於: Journal of the Chinese Institute of Electrical Engineering, Transactions of the Chinese Institute of Engineers, Series E/Chung KuoTien Chi Kung Chieng Hsueh K'an. 8, 4, p. 365-376 12 p.

  研究成果: Article › 同行評審

  • Shift registers 100%
  • Feedback 50%
  • Built-in self test 16%
  • Clocks 11%
  • Costs 5%

• Reduction of power consumption in scan-based circuits during test application by an input control technique

  Huang, T. C. & Lee, K. J., 2001 7月, 於: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 20, 7, p. 911-917 7 p.

  研究成果: Article › 同行評審

  • Electric power utilization 100%
  • Networks (circuits) 74%
  • Experiments 9%
  46 引文 斯高帕斯（Scopus）

• Token scan cell for low power testing

  Huang, T. C. & Lee, K. J., 2001 5月 24, 於: Electronics Letters. 37, 11, p. 678-679 2 p.

  研究成果: Article › 同行評審

  • Flip flop circuits 100%
  • Networks (circuits) 47%
  • Testing 44%
  • Clocks 36%
  • Scanning 33%
  5 引文 斯高帕斯（Scopus）
• 2000

  Reducing test application time by scan flip-flops sharing

  Chang, S. C., Lee, K. J., Wu, Z. Z. & Jone, W. B., 2000, 於: IEE Proceedings: Computers and Digital Techniques. 147, 1, p. 42-48 7 p.

  研究成果: Article › 同行評審

  • Flip flop circuits 100%
  • Flip 97%
  • Networks (circuits) 47%
  • Fault 28%
  • Benchmark 24%
  7 引文 斯高帕斯（Scopus）
• 1999

  A current-mode testable design of operational transconductance amplifier-capacitor filters

  Lee, K. J., Wang, W. C. & Huang, K. S., 1999, 於: IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing. 46, 4, p. 401-413 13 p.

  研究成果: Article › 同行評審

  • Operational amplifiers 100%
  • Capacitors 74%
  • Error detection 62%
  • Networks (circuits) 51%
  • High definition television 23%
  28 引文 斯高帕斯（Scopus）

• BIFEST: A built-in intermediate fault effect sensing and test generation system for cmos bridging faults

  Lee, K. J., Tang, J. J. & Huang, T. C., 1999, 於: ACM Transactions on Design Automation of Electronic Systems. 4, 2, p. 194-218 25 p.

  研究成果: Article › 同行評審

  開啟存取

  • Electric potential 100%
  • Monitoring 36%
  • Networks (circuits) 35%
  • Testing 33%
  • Sensors 33%
  1 引文 斯高帕斯（Scopus）

• Broadcasting test patterns to multiple circuits

  Lee, K. J., Chen, J. J. & Huang, C. H., 1999 12月, 於: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 18, 12, p. 1793-1802 10 p.

  研究成果: Article › 同行評審

  • Broadcasting 100%
  • Sequential circuits 84%
  • Compaction 55%
  • Networks (circuits) 53%
  • Automatic test pattern generation 49%
  51 引文 斯高帕斯（Scopus）

• Embedded march algorithm test pattern generator for memory testing

  Wang, W. L., Lee, K-J. & Wang, J. F., 1999, 於: International Symposium on VLSI Technology, Systems, and Applications, Proceedings. p. 211-214 4 p.

  研究成果: Article › 同行評審

  • test pattern generators 100%
  • systems-on-a-chip 32%
  • Data storage equipment 26%
  • Testing 22%
  • hardware 21%
  2 引文 斯高帕斯（Scopus）
• 1998

  A built-in current sensor based on current-mode design

  Lee, K. J. & Tang, J. J., 1998, 於: IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing. 45, 1, p. 133-137 5 p.

  研究成果: Article › 同行評審

  • Sensors 100%
  • Testing 33%
  • Temperature 26%
  11 引文 斯高帕斯（Scopus）

• A general structure of feedback shift registers for built-in self test

  Lee, K. J., Wang, W. L. & Wang, J. F. A., 1998 9月, 於: Journal of Information Science and Engineering. 14, 3, p. 645-667 23 p.

  研究成果: Article › 同行評審

  • Built-in Self-test 100%
  • Shift registers 64%
  • Built-in self test 64%
  • Feedback 32%
  • Signature 22%