• 1342 引文
  • 19 h-指數
1990 …2020
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研究成果 1990 2019

篩選
Article
2019
Automatic test pattern generation
Compaction
Networks (circuits)
Trimming
Fault detection
1 引文 (Scopus)
Built-in self test
Failure analysis
Clocks
Controllers
Networks (circuits)
2018
2 引文 (Scopus)

A Hybrid Multicast Routing Approach with Enhanced Methods for Mesh-Based Networks-on-Chip

Wu, C. W., Lee, K-J. & Su, A. P., 2018 九月 1, 於 : IEEE Transactions on Computers. 67, 9, p. 1231-1245 15 p., 8309347.

研究成果: Article

Multicast Routing
Routing algorithms
Deadlock
Routing Algorithm
Mesh

A Repair-for-Diagnosis Methodology for Logic Circuits

Wu, C. H., Lin, S. L., Lee, K-J. & Reddy, S. M., 2018 十一月 1, 於 : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 26, 11, p. 2254-2267 14 p., 8423443.

研究成果: Article

Logic circuits
Repair
Defects
Networks (circuits)
Failure analysis
2017
2 引文 (Scopus)
Crosstalk
Topology
Silicon
Testing
9 引文 (Scopus)
Networks (circuits)
Switches
Flip flop circuits
Data reduction
2015

A high-performance SoC debug platform

Liu, K. K., Hsu, W. H. & Lee, K-J., 2015 一月 1, 於 : Smart Science. 3, 4, p. 202-208 7 p.

研究成果: Article

High Performance
Debugging
Design Automation
Automation
Trigger
2014
23 引文 (Scopus)
Testing
Refining
Networks (circuits)
4 引文 (Scopus)

Efficient LFSR Reseeding Based on Internal-Response Feedback

Lien, W. C., Lee, K-J., Hsieh, T. Y. & Chakrabarty, K., 2014 十二月 3, 於 : Journal of Electronic Testing: Theory and Applications (JETTA). 30, 6, p. 673-685 13 p.

研究成果: Article

Feedback
Seed
Networks (circuits)
Built-in self test
Integrated circuits
3 引文 (Scopus)
Network protocols
Interfaces (computer)
Communication
2013
10 引文 (Scopus)
Seed
Networks (circuits)
Inventory control
Data storage equipment
5 引文 (Scopus)

Counter-based output selection for test response compaction

Lien, W. C., Lee, K-J., Hsieh, T. Y., Chakrabarty, K. & Wu, Y. H., 2013 一月 7, 於 : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 32, 1, p. 152-164 13 p., 6387700.

研究成果: Article

Compaction
Hardware
Networks (circuits)
2012
9 引文 (Scopus)
Networks (circuits)
Automatic test pattern generation
Testing
2011
5 引文 (Scopus)
Networks (circuits)
28 引文 (Scopus)
Pipelines
Testing
Macros
Data storage equipment
13 引文 (Scopus)

Programmable system-on-chip for silicon prototyping

Huang, C. M., Wu, C. M., Yang, C. C., Chen, S. L., Chen, C. S., Wang, J. J., Lee, K. J. & Wey, C. L., 2011 三月 1, 於 : IEEE Transactions on Industrial Electronics. 58, 3, p. 830-838 9 p., 4926187.

研究成果: Article

Silicon
System-on-chip
Costs
Fabrication
14 引文 (Scopus)

Test response compaction via output bit selection

Lee, K-J., Lien, W. C. & Hsieh, T. Y., 2011 十月 1, 於 : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 30, 10, p. 1534-1544 11 p., 6022010.

研究成果: Article

Compaction
Networks (circuits)
Automatic test pattern generation
Shift registers
Set theory
2010
11 引文 (Scopus)

On-chip SOC test platform design based on IEEE 1500 standard

Lee, K-J., Hsieh, T. Y., Chang, C. Y., Hong, Y. T. & Huang, W. C., 2010 七月 1, 於 : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 18, 7, p. 1134-1139 6 p., 5229351.

研究成果: Article

Built-in self test
Data storage equipment
Testing
Embedded systems
Field programmable gate arrays (FPGA)
2008
17 引文 (Scopus)

An error rate based test methodology to support error-tolerance

Hsieh, T. Y., Lee, K-J. & Breuer, M. A., 2008 三月 1, 於 : IEEE Transactions on Reliability. 57, 1, p. 204-214 11 p.

研究成果: Article

Sampling
Networks (circuits)
2007

A design automation system for SOC test platform

Huang, W. C., Lee, K-J., Chang, C. Y. & Wu, Y. H., 2007 六月 1, 於 : International Journal of Electrical Engineering. 14, 3, p. 219-227 9 p.

研究成果: Article

Automation
User interfaces
Controllers
Testing
1 引文 (Scopus)

Preventing over-detection of acceptable faults for yield enhancement

Hsieh, T. Y., Lee, K-J. & Breuer, M. A., 2007 六月, 於 : International Journal of Electrical Engineering. 14, 3, p. 185-193 9 p.

研究成果: Article

Degradation
Defects
Testing
2004
49 引文 (Scopus)

Test power reduction with multiple capture orders

Lee, K-J., Hsu, S. J. & Ho, C. M., 2004, 於 : Proceedings of the Asian Test Symposium. p. 26-31 6 p.

研究成果: Article

Energy dissipation
Networks (circuits)
Testing
2003
Clocks
Demultiplexing
Broadcasting
Compression testing
Shift registers
23 引文 (Scopus)
Clocks
Energy dissipation
Networks (circuits)
Electric power utilization
Testing
2002
3 引文 (Scopus)

A 0.5 μm concurrent testable chip of a fifth-order gm-C filter

Lee, K-J. & Wang, W. C., 2002 九月 1, 於 : Analog Integrated Circuits and Signal Processing. 32, 3, p. 231-247 17 p.

研究成果: Article

Networks (circuits)
Error detection
Low pass filters
Testing
Electric potential
5 引文 (Scopus)

A current-mode BIST structure of DACs

Wen, Y. C. & Lee, K-J., 2002 四月 1, 於 : Measurement: Journal of the International Measurement Confederation. 31, 3, p. 147-163 17 p.

研究成果: Article

Built-in Self-test
self tests
Built-in self test
Voltage
Nonlinearity
9 引文 (Scopus)

An efficient BIST method for distributed small buffers

Jone, W. B., Huang, D. C., Wu, S. C. & Lee, K. J., 2002 八月 1, 於 : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 10, 4, p. 512-514 3 p.

研究成果: Article

Data storage equipment
Testing
Hardware
Built-in self test
Shift registers
Feedback
Logic circuits
Clocks
2 引文 (Scopus)
Networks (circuits)
Testing
5 引文 (Scopus)

A low-power LFSR architecture

Huang, T. C. & Lee, K-J., 2001 一月 1, 於 : Proceedings of the Asian Test Symposium. 1 p., 80.

研究成果: Article

Built-in self test
Clocks
Networks (circuits)
16 引文 (Scopus)
Data storage equipment
Testing
Shift registers
Hardware
42 引文 (Scopus)
Electric power utilization
Networks (circuits)
Experiments
5 引文 (Scopus)

Token scan cell for low power testing

Huang, T. C. & Lee, K-J., 2001 五月 24, 於 : Electronics Letters. 37, 11, p. 678-679 2 p.

研究成果: Article

Flip flop circuits
Networks (circuits)
Testing
Clocks
Scanning
2000
2 引文 (Scopus)
Built-in self test
Shift registers
Feedback
Clocks
Costs
11 引文 (Scopus)
Testing
Integrated circuit design
System-on-chip
Intellectual property core
7 引文 (Scopus)

Reducing test application time by scan flip-flops sharing

Chang, S. C., Lee, K-J., Wu, Z. Z. & Jone, W. B., 2000 一月 1, 於 : IEE Proceedings: Computers and Digital Techniques. 147, 1, p. 42-48 7 p.

研究成果: Article

Flip flop circuits
Flip
Sharing
Networks (circuits)
Fault
1999
26 引文 (Scopus)
Operational amplifiers
Capacitors
Error detection
Networks (circuits)
High definition television
1 引文 (Scopus)
Electric potential
Networks (circuits)
Monitoring
Sensors
Testing
49 引文 (Scopus)

Broadcasting test patterns to multiple circuits

Lee, K-J., Chen, J. J. & Huang, C. H., 1999 十二月 1, 於 : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 18, 12, p. 1793-1802 10 p.

研究成果: Article

Broadcasting
Sequential circuits
Networks (circuits)
Compaction
Automatic test pattern generation
2 引文 (Scopus)
test pattern generators
systems-on-a-chip
Data storage equipment
Testing
hardware
1998
10 引文 (Scopus)
Sensors
Testing
Temperature

A general structure of feedback shift registers for built-in self test

Lee, K. J., Wang, W. L. & Wang, J. F. A., 1998 九月 1, 於 : Journal of Information Science and Engineering. 14, 3, p. 645-667 23 p.

研究成果: Article

Built-in self test
Shift registers
Feedback
Flip flop circuits
Polynomials
Logic design
Testing
Automatic test pattern generation
Directed graphs
Data structures
20 引文 (Scopus)

BIST structure for DAC testing

Wen, Y. C. & Lee, K-J., 1998 六月 11, 於 : Electronics Letters. 34, 12, p. 1173-1174 2 p.

研究成果: Article

Built-in self test
Digital to analog conversion
Testing
Electric potential
1 引文 (Scopus)
Switched capacitor filters
Error detection
Fault tolerance
tolerance
Networks (circuits)
1997
5 引文 (Scopus)

Concurrent test method for OTA-C filters

Lee, K-J., Huang, K. S., Wang, W. C., Pookaiyaudom, S., Sitdhikorn, R. & Thanachayanont, A., 1997 一月 2, 於 : Electronics Letters. 33, 1, p. 1-3 3 p.

研究成果: Article

Networks (circuits)
Electric potential