高國興

Tang, Y. T., Fan, C. L., Kao, Y. C., Modolo, N., Su, C. J., Wu, T. L., Kao, K. H., Wu, P. J., Hsaio, S. W., Useinov, A., Su, P., Wu, W. F., Huang, G. W., Shieh, J. M., Yeh, W. K. & Wang, Y. H., 2019 六月, 2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., p. T222-T223 8776508. (Digest of Technical Papers - Symposium on VLSI Technology; 卷 2019-June).

研究成果: Conference contribution

Demonstration of annealing-free metal-insulator-semiconductor (mis) ohmic contacts on a gan substrate using low work-function metal ytterbium (yb) and al₂o₃ interfacial layer

Wu, T. L., Tseng, Y. Y., Huang, C. F., Chen, Z. S., Lin, C. C., Chung, C. J., Huang, P. K. & Kao, K. H., 2019 五月, WiPDA Asia 2019 - IEEE Workshop on Wide Bandgap Power Devices and Applications in Asia. Institute of Electrical and Electronics Engineers Inc., 8760323. (WiPDA Asia 2019 - IEEE Workshop on Wide Bandgap Power Devices and Applications in Asia).

研究成果: Conference contribution

Fabrication of omega-gated negative capacitance finfets and SRAM

Sung, P. J., Su, C. J., Lu, D. D., Luo, S. X., Kao, K. H., Ciou, J. Y., Jao, C. Y., Hsu, H. S., Wang, C. J., Hong, T. C., Liao, T. H., Fang, C. C., Wang, Y. S., Huang, H. F., Li, J. H., Huang, Y. C., Hsueh, F. K., Wu, C. T., Ma, W. C. Y., Huang, K. P. 及其他6, Lee, Y. J., Chao, T. S., Li, J. Y., Wu, W. F., Yeh, W. K. & Wang, Y. H., 2019 四月, 2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019. Institute of Electrical and Electronics Engineers Inc., 8804663. (2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019).

研究成果: Conference contribution

Impact of Semiconductor Permittivity Reduction on Electrical Characteristics of Nanoscale MOSFETs

Chen, S. H., Lian, S. W., Wu, T. R., Chang, T. R., Liou, J. M., Lu, D. D., Kao, K. H., Chen, N. Y., Lee, W. J. & Tsai, J. H., 2019 六月, 於 : IEEE Transactions on Electron Devices. 66, 6, p. 2509-2512 4 p., 8704283.

研究成果: Article

Voltage Transfer Characteristic Matching by Different Nanosheet Layer Numbers of Vertically Stacked Junctionless CMOS Inverter for SoP/3D-ICs applications

Sung, P. J., Chang, C. Y., Chen, L. Y., Kao, K. H., Su, C. J., Liao, T. H., Fang, C. C., Wang, C. J., Hong, T. C., Jao, C. Y., Hsu, H. S., Luo, S. X., Wang, Y. S., Huang, H. F., Li, J. H., Huang, Y. C., Hsueh, F. K., Wu, C. T., Huang, Y. M., Hou, F. J. 及其他16, Luo, G. L., Huang, Y. C., Shen, Y. L., Ma, W. C. Y., Huang, K. P., Lin, K. L., Samukawa, S., Li, Y., Huang, G. W., Lee, Y. J., Li, J. Y., Wu, W. F., Shieh, J. M., Chao, T. S., Yeh, W. K. & Wang, Y. H., 2019 一月 16, 2018 IEEE International Electron Devices Meeting, IEDM 2018. Institute of Electrical and Electronics Engineers Inc., p. 21.4.1-21.4.4 8614553. (Technical Digest - International Electron Devices Meeting, IEDM; 卷 2018-December).

研究成果: Conference contribution