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研究成果

2020

Impact of the polarization on time-dependent dielectric breakdown in ferroelectric Hf0.5Zr0.5O2 on Ge substrates

Yang, T. H., Su, C. J., Wang, Y. S., Kao, K. H., Lee, Y. J. & Wu, T. L., 2020 四月 1, 於 : Japanese Journal of Applied Physics. 59, SG, SGGB08.

研究成果: Article

2019

A Comprehensive Kinetical Modeling of Polymorphic Phase Distribution of Ferroelectric-Dielectrics and Interfacial Energy Effects on Negative Capacitance FETs

Tang, Y. T., Fan, C. L., Kao, Y. C., Modolo, N., Su, C. J., Wu, T. L., Kao, K. H., Wu, P. J., Hsaio, S. W., Useinov, A., Su, P., Wu, W. F., Huang, G. W., Shieh, J. M., Yeh, W. K. & Wang, Y. H., 2019 六月, 2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., p. T222-T223 8776508. (Digest of Technical Papers - Symposium on VLSI Technology; 卷 2019-June).

研究成果: Conference contribution

Demonstration of annealing-free metal-insulator-semiconductor (mis) ohmic contacts on a gan substrate using low work-function metal ytterbium (yb) and al2o3 interfacial layer

Wu, T. L., Tseng, Y. Y., Huang, C. F., Chen, Z. S., Lin, C. C., Chung, C. J., Huang, P. K. & Kao, K. H., 2019 五月, WiPDA Asia 2019 - IEEE Workshop on Wide Bandgap Power Devices and Applications in Asia. Institute of Electrical and Electronics Engineers Inc., 8760323. (WiPDA Asia 2019 - IEEE Workshop on Wide Bandgap Power Devices and Applications in Asia).

研究成果: Conference contribution

Fabrication of omega-gated negative capacitance finfets and SRAM

Sung, P. J., Su, C. J., Lu, D. D., Luo, S. X., Kao, K. H., Ciou, J. Y., Jao, C. Y., Hsu, H. S., Wang, C. J., Hong, T. C., Liao, T. H., Fang, C. C., Wang, Y. S., Huang, H. F., Li, J. H., Huang, Y. C., Hsueh, F. K., Wu, C. T., Ma, W. C. Y., Huang, K. P. 及其他6, Lee, Y. J., Chao, T. S., Li, J. Y., Wu, W. F., Yeh, W. K. & Wang, Y. H., 2019 四月, 2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019. Institute of Electrical and Electronics Engineers Inc., 8804663. (2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019).

研究成果: Conference contribution

2 引文 斯高帕斯(Scopus)

First Demonstration of CMOS Inverter and 6T-SRAM Based on GAA CFETs Structure for 3D-IC Applications

Chang, S. W., Li, J. H., Huang, M. K., Huang, Y. C., Huang, S. T., Wang, H. C., Huang, Y. J., Wang, J. Y., Yu, L. W., Huang, Y. F., Hsueh, F. K., Sung, P. J., Wu, C. T., Ma, W. C. Y., Kao, K. H., Lee, Y. J., Lin, C. L., Chuang, R. W., Huang, K. P., Samukawa, S. 及其他16, Li, Y., Lee, W. H., Chu, T. Y., Chao, T. S., Huang, G. W., Wu, W. F., Li, J. Y., Shieh, J. M., Yeh, W. K., Wang, Y. H., Lu, D. D., Wang, C. J., Lin, N. C., Su, C. J., Lo, S. H. & Huang, H. F., 2019 十二月, 2019 IEEE International Electron Devices Meeting, IEDM 2019. Institute of Electrical and Electronics Engineers Inc., 8993525. (Technical Digest - International Electron Devices Meeting, IEDM; 卷 2019-December).

研究成果: Conference contribution

2 引文 斯高帕斯(Scopus)

Impact of Semiconductor Permittivity Reduction on Electrical Characteristics of Nanoscale MOSFETs

Chen, S. H., Lian, S. W., Wu, T. R., Chang, T. R., Liou, J. M., Lu, D. D., Kao, K. H., Chen, N. Y., Lee, W. J. & Tsai, J. H., 2019 六月, 於 : IEEE Transactions on Electron Devices. 66, 6, p. 2509-2512 4 p., 8704283.

研究成果: Article

2 引文 斯高帕斯(Scopus)

Voltage Transfer Characteristic Matching by Different Nanosheet Layer Numbers of Vertically Stacked Junctionless CMOS Inverter for SoP/3D-ICs applications

Sung, P. J., Chang, C. Y., Chen, L. Y., Kao, K. H., Su, C. J., Liao, T. H., Fang, C. C., Wang, C. J., Hong, T. C., Jao, C. Y., Hsu, H. S., Luo, S. X., Wang, Y. S., Huang, H. F., Li, J. H., Huang, Y. C., Hsueh, F. K., Wu, C. T., Huang, Y. M., Hou, F. J. 及其他16, Luo, G. L., Huang, Y. C., Shen, Y. L., Ma, W. C. Y., Huang, K. P., Lin, K. L., Samukawa, S., Li, Y., Huang, G. W., Lee, Y. J., Li, J. Y., Wu, W. F., Shieh, J. M., Chao, T. S., Yeh, W. K. & Wang, Y. H., 2019 一月 16, 2018 IEEE International Electron Devices Meeting, IEDM 2018. Institute of Electrical and Electronics Engineers Inc., p. 21.4.1-21.4.4 8614553. (Technical Digest - International Electron Devices Meeting, IEDM; 卷 2018-December).

研究成果: Conference contribution

4 引文 斯高帕斯(Scopus)
2018

A comprehensive study of polymorphic phase distribution of ferroelectric-dielectrics and interfacial layer effects on negative capacitance FETs for Sub-5 nm node

Tang, Y. T., Su, C. J., Wang, Y. S., Kao, K. H., Wu, T. L., Sung, P. J., Hou, F. J., Wang, C. J., Yeh, M. S., Lee, Y. J., Wu, W. F., Huang, G. W., Shieh, J. M., Yeh, W. K. & Wang, Y. H., 2018 十月 25, 2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018. Institute of Electrical and Electronics Engineers Inc., p. 45-46 2 p. 8510696. (Digest of Technical Papers - Symposium on VLSI Technology; 卷 2018-June).

研究成果: Conference contribution

2 引文 斯高帕斯(Scopus)

An FET with a Source Tunneling Barrier Showing Suppressed Short-Channel Effects for Low-Power Applications

Hsieh, Y. F., Chen, S. H., Chen, N. Y., Lee, W. J., Tsai, J. H., Chen, C. N., Chiang, M-H., Lu, D. & Kao, K-H., 2018 三月 1, 於 : IEEE Transactions on Electron Devices. 65, 3, p. 855-859 5 p.

研究成果: Article

1 引文 斯高帕斯(Scopus)

Ge nanowire FETs with HfZrOx ferroelectric gate stack exhibiting SS of sub-60 mV/dec and biasing effects on ferroelectric reliability

Su, C. J., Hong, T. C., Tsou, Y. C., Hou, F. J., Sung, P. J., Yeh, M. S., Wan, C. C., Kao, K. H., Tang, Y. T., Chiu, C. H., Wang, C. J., Chung, S. T., You, T. Y., Huang, Y. C., Wu, C. T., Lin, K. L., Luo, G. L., Huang, K. P., Lee, Y. J., Chao, T. S. 及其他5, Wu, W. F., Huang, G. W., Shieh, J. M., Yeh, W. K. & Wang, Y. H., 2018 一月 23, 2017 IEEE International Electron Devices Meeting, IEDM 2017. Institute of Electrical and Electronics Engineers Inc., p. 15.4.1-15.4.4 (Technical Digest - International Electron Devices Meeting, IEDM).

研究成果: Conference contribution

9 引文 斯高帕斯(Scopus)

Junctionless FETs with a Fin Body for Multi-VTH and Dynamic Threshold Operation

Kumar, M. P. V., Lin, J. Y., Kao, K. H. & Chao, T. S., 2018 八月, 於 : IEEE Transactions on Electron Devices. 65, 8, p. 3535-3542 8 p., 8399532.

研究成果: Article

4 引文 斯高帕斯(Scopus)

Significance of Multivalley and Nonparabolic Band Structure for GeSn TFET Simulation

Kumar, K., Hsieh, Y. F., Liao, J. H., Kao, K. H. & Wang, Y. H., 2018 十月, 於 : IEEE Transactions on Electron Devices. 65, 10, p. 4709-4715 7 p., 8445683.

研究成果: Article

3 引文 斯高帕斯(Scopus)
2017

A dopingless FET with metal-insulator-semiconductor contacts

Kao, K. H. & Chen, L. Y., 2017 一月, 於 : IEEE Electron Device Letters. 38, 1, p. 5-8 4 p., 7742896.

研究成果: Article

11 引文 斯高帕斯(Scopus)

High performance complementary Ge peaking FinFETs by room temperature neutral beam oxidation for sub-7 nm technology node applications

Lee, Y. J., Hong, T. C., Hsueh, F. K., Sung, P. J., Chen, C. Y., Chuang, S. S., Cho, T. C., Noda, S., Tsou, Y. C., Kao, K. H., Wu, C. T., Yu, T. Y., Jian, Y. L., Su, C. J., Huang, Y. M., Huang, W. H., Chen, B. Y., Chen, M. C., Huang, K. P., Li, J. Y. 及其他10, Chen, M. J., Li, Y., Samukawa, S., Wu, W. F., Huang, G. W., Shieh, J. M., Tseng, T. Y., Chao, T. S., Wang, Y. H. & Yeh, W. K., 2017 一月 31, 2016 IEEE International Electron Devices Meeting, IEDM 2016. Institute of Electrical and Electronics Engineers Inc., p. 33.5.1-33.5.4 7838535. (Technical Digest - International Electron Devices Meeting, IEDM).

研究成果: Conference contribution

3 引文 斯高帕斯(Scopus)

Improving the Electrical Performance of a Quantum Well FET with a Shell Doping Profile by Heterojunction Optimization

Kumar, M. P. V., Hu, C. Y., Walke, A. M., Kao, K. H. & Chao, T. S., 2017 九月, 於 : IEEE Transactions on Electron Devices. 64, 9, p. 3563-3568 6 p., 7990547.

研究成果: Article

3 引文 斯高帕斯(Scopus)

Nano-scaled Ge FinFETs with low temperature ferroelectric HfZrO x on specific interfacial layers exhibiting 65% S.S. reduction and improved I ON

Su, C. J., Tang, Y. T., Tsou, Y. C., Sung, P. J., Hou, F. J., Wang, C. J., Chung, S. T., Hsieh, C. Y., Yeh, Y. S., Hsueh, F. K., Kao, K-H., Chuang, S. S., Wu, C. T., You, T. Y., Jian, Y. L., Chou, T. H., Shen, Y. L., Chen, B. Y., Luo, G. L., Hong, T. C. 及其他10, Huang, K. P., Chen, M. C., Lee, Y. J., Chao, T. S., Tseng, T. Y., Wu, W. F., Huang, G. W., Shieh, J. M., Yeh, W. K. & Wang, Y-H., 2017 七月 31, 2017 Symposium on VLSI Technology, VLSI Technology 2017. Institute of Electrical and Electronics Engineers Inc., p. T152-T153 7998159. (Digest of Technical Papers - Symposium on VLSI Technology).

研究成果: Conference contribution

16 引文 斯高帕斯(Scopus)

Ultra-shallow junction formation by monolayer doping process in single crystalline Si and Ge for future CMOS devices

Chuang, S. S., Cho, T. C., Sung, P. J., Kao, K. H., Chen, H. J. H., Lee, Y. J., Current, M. I. & Tseng, T. Y., 2017 一月 1, 於 : ECS Journal of Solid State Science and Technology. 6, 5, p. P350-P355

研究成果: Article

7 引文 斯高帕斯(Scopus)

Undoped and doped junctionless FETs: Source/drain contacts and immunity to random dopant fluctuation

Chen, L. Y., Hsieh, Y. F. & Kao, K-H., 2017 六月 1, 於 : IEEE Electron Device Letters. 38, 6, p. 708-711 4 p., 7891976.

研究成果: Article

4 引文 斯高帕斯(Scopus)

Undoped SiGe FETs with metal-insulator-semiconductor contacts

Chen, L. Y., Hsieh, Y. F. & Kao, K. H., 2017 十二月 29, 2017 Silicon Nanoelectronics Workshop, SNW 2017. Institute of Electrical and Electronics Engineers Inc., p. 95-96 2 p. 8242314. (2017 Silicon Nanoelectronics Workshop, SNW 2017; 卷 2017-January).

研究成果: Conference contribution

2016

ELECTROMECHANICAL DEVICE WITH LIGHT GATING AND OPERATIONAL METHODS THEREOF

貢獻的翻譯標題: 光驅動機械式電子元件及其操作方法Kao, K-H., 2016 五月 16, 專利號 I552343

研究成果: Patent

2015

A novel junctionless FinFET structure with sub-5nm shell doping profile by molecular monolayer doping and microwave annealing

Lee, Y. J., Cho, T. C., Kao, K-H., Sung, P. J., Hsueh, F. K., Huang, P. C., Wu, C. T., Hsu, S. H., Huang, W. H., Chen, H. C., Li, Y., Current, M. I., Hengstebeck, B., Marino, J., Büyüklimanli, T., Shieh, J. M., Chao, T. S., Wu, W. F. & Yeh, W. K., 2015 二月 20, 於 : Technical Digest - International Electron Devices Meeting, IEDM. 2015-February, February, p. 32.7.1-32.7.4 7047158.

研究成果: Conference article

20 引文 斯高帕斯(Scopus)

Diamond-shaped Ge and Ge0.9Si0.1 gate-all-around nanowire FETs with four {111} facets by dry etch technology

Lee, Y. J., Hou, F. J., Chuang, S. S., Hsueh, F. K., Kao, K. H., Sung, P. J., Yuan, W. Y., Yao, J. Y., Lu, Y. C., Lin, K. L., Wu, C. T., Chen, H. C., Chen, B. Y., Huang, G. W., Chen, H. J. H., Li, J. Y., Li, Y., Samukawa, S., Chao, T. S., Tseng, T. Y. 及其他3, Wu, W. F., Hou, T. H. & Yeh, W. K., 2015 二月 16, 2015 IEEE International Electron Devices Meeting, IEDM 2015. Institute of Electrical and Electronics Engineers Inc., p. 15.1.1-15.1.4 7409701. (Technical Digest - International Electron Devices Meeting, IEDM; 卷 2016-February).

研究成果: Conference contribution

6 引文 斯高帕斯(Scopus)

High performance poly Si junctionless transistors with sub-5nm conformally doped layers by molecular monolayer doping and microwave incorporating CO2 laser annealing for 3D stacked ICs applications

Lee, Y. J., Cho, T. C., Sung, P. J., Kao, K. H., Hsueh, F. K., Hou, F. J., Chen, P. C., Chen, H. C., Wu, C. T., Hsu, S. H., Chen, Y. J., Huang, Y. M., Hou, Y. F., Huang, W. H., Yang, C. C., Chen, B. Y., Lin, K. L., Chen, M. C., Shen, C. H., Huang, G. W. 及其他8, Huang, K. P., Current, M. I., Li, Y., Samukawa, S., Wu, W. F., Shieh, J. M., Chao, T. S. & Yeh, W. K., 2015 二月 16, 2015 IEEE International Electron Devices Meeting, IEDM 2015. Institute of Electrical and Electronics Engineers Inc., p. 6.2.1-6.2.4 7409638. (Technical Digest - International Electron Devices Meeting, IEDM; 卷 2016-February).

研究成果: Conference contribution

14 引文 斯高帕斯(Scopus)

Impacts of the Shell Doping Profile on the Electrical Characteristics of Junctionless FETs

Kumar, M. P. V., Hu, C. Y., Kao, K-H., Lee, Y. J. & Chao, T. S., 2015 九月 7, 於 : IEEE Transactions on Electron Devices. 62, 11, p. 3541-3546 6 p., 7244201.

研究成果: Article

20 引文 斯高帕斯(Scopus)

Perspective of tunnel-FET for future low-power technology nodes

Verhulst, A. S., Verreck, D., Smets, Q., Kao, K. H., Van De Put, M., Rooyackers, R., Sorée, B., Vandooren, A., De Meyer, K., Groeseneken, G., Heyns, M. M., Mocuta, A., Collaert, N. & Thean, A. V. Y., 2015 二月 20, 2014 IEEE International Electron Devices Meeting, IEDM 2014. February 編輯 Institute of Electrical and Electronics Engineers Inc., p. 30.2.1-30.2.4 7047140. (Technical Digest - International Electron Devices Meeting, IEDM; 卷 2015-February, 編號 February).

研究成果: Conference contribution

11 引文 斯高帕斯(Scopus)
2014

Compressively strained SiGe band-to-band tunneling model calibration based on p-i-n diodes and prospect of strained SiGe tunneling field-effect transistors

Kao, K-H., Verhulst, A. S., Rooyackers, R., Douhard, B., Delmotte, J., Bender, H., Richard, O., Vandervorst, W., Simoen, E., Hikavyy, A., Loo, R., Arstila, K., Collaert, N., Thean, A., Heyns, M. M. & Meyer, K. D., 2014 十二月 7, 於 : Journal of Applied Physics. 116, 21, 214506.

研究成果: Article

16 引文 斯高帕斯(Scopus)

Fabrication and analysis of a Si/Si0.55Ge0.45 heterojunction line tunnel FET

Walke, A. M., Vandooren, A., Rooyackers, R., Leonelli, D., Hikavyy, A., Loo, R., Verhulst, A. S., Kao, K. H., Huyghebaert, C., Groeseneken, G., Rao, V. R., Bhuwalka, K. K., Heyns, M. M., Collaert, N. & Thean, A. V. Y., 2014 三月, 於 : IEEE Transactions on Electron Devices. 61, 3, p. 707-715 9 p., 6727530.

研究成果: Article

56 引文 斯高帕斯(Scopus)

Tensile strained Ge tunnel field-effect transistors: k · p material modeling and numerical device simulation

Kao, K. H., Verhulst, A. S., Van De Put, M., Vandenberghe, W. G., Soree, B., Magnus, W. & De Meyer, K., 2014 一月 1, 於 : Journal of Applied Physics. 115, 4, 044505.

研究成果: Article

30 引文 斯高帕斯(Scopus)
2013

A simulation study on process sensitivity of a line tunnel field-effect transistor

Walke, A. M., Vandenberghe, W. G., Kao, K. H., Vandooren, A. & Groeseneken, G., 2013 二月 15, 於 : IEEE Transactions on Electron Devices. 60, 3, p. 1019-1027 9 p., 6461086.

研究成果: Article

4 引文 斯高帕斯(Scopus)

Counterdoped pocket thickness optimization of gate-on-source-only tunnel FETs

Kao, K-H., Verhulst, A. S., Vandenberghe, W. G. & De Meyer, K., 2013 一月 1, 於 : IEEE Transactions on Electron Devices. 60, 1, p. 6-12 7 p., 6359896.

研究成果: Article

18 引文 斯高帕斯(Scopus)

Erratum: Quantum mechanical performance predictions of p-n-i-n versus pocketed line tunnel field-effect transistors (IEEE Transactions on Electron Devices (2013) 60:7 (2128-2134))

Verreck, D., Verhulst, A. S., Kao, K. H., Vandenberghe, W. G., De Meyer, K. & Groeseneken, G., 2013 十月 2, 於 : IEEE Transactions on Electron Devices. 60, 10, 1 p., 6588911.

研究成果: Comment/debate

Quantum mechanical performance predictions of p-n-i-n versus pocketed line tunnel field-effect transistors

Verreck, D., Verhulst, A. S., Kao, K. H., Vandenberghe, W. G., De Meyer, K. & Groeseneken, G., 2013 六月 7, 於 : IEEE Transactions on Electron Devices. 60, 7, p. 2128-2134 7 p., 6523085.

研究成果: Article

43 引文 斯高帕斯(Scopus)
2012

A model determining optimal doping concentration and material's band gap of tunnel field-effect transistors

Vandenberghe, W. G., Verhulst, A. S., Kao, K. H., Meyer, K. D., Sorée, B., Magnus, W. & Groeseneken, G., 2012 五月 7, 於 : Applied Physics Letters. 100, 19, 193509.

研究成果: Article

30 引文 斯高帕斯(Scopus)

Direct and indirect band-to-band tunneling in germanium-based TFETs

Kao, K-H., Verhulst, A. S., Vandenberghe, W. G., Soree, B., Groeseneken, G. & De Meyer, K., 2012 二月 1, 於 : IEEE Transactions on Electron Devices. 59, 2, p. 292-301 10 p., 6096396.

研究成果: Article

237 引文 斯高帕斯(Scopus)

Modeling the impact of junction angles in tunnel field-effect transistors

Kao, K-H., Verhulst, A. S., Vandenberghe, W. G., Sorée, B., Groeseneken, G. & Meyer, K. D., 2012 三月 1, 於 : Solid-State Electronics. 69, p. 31-37 7 p.

研究成果: Article

9 引文 斯高帕斯(Scopus)

Optimization of gate-on-source-only tunnel FETs with counter-doped pockets

Kao, K. H., Verhulst, A. S., Vandenberghe, W. G., Sorée, B., Magnus, W., Leonelli, D., Groeseneken, G. & De Meyer, K., 2012 七月 3, 於 : IEEE Transactions on Electron Devices. 59, 8, p. 2070-2077 8 p., 6226449.

研究成果: Article

77 引文 斯高帕斯(Scopus)

SiGe band-to-band tunneling calibration based on p-i-n diodes: Fabrication, measurement and simulation

Kao, K. H., Verhulst, A. S., Rooyackers, R., Hikavyy, A., Simoen, E., Arstila, K., Douhard, B., Loo, R., Milenin, A. P., Tolle, J., Dekkers, H., Machkaoutsan, V., Maes, J. W., De Meyer, K., Collaert, N., Heyns, M. M., Huyghebaert, C. & Thean, A., 2012 十二月 1, SiGe, Ge, and Related Compounds 5: Materials, Processing, and Devices. 9 編輯 p. 965-970 6 p. (ECS Transactions; 卷 50, 編號 9).

研究成果: Conference contribution

4 引文 斯高帕斯(Scopus)
2011

Si-based tunnel field-effect transistors for low-power nano-electronics

Verhulst, A. S., Vandenberghe, W. G., Leonelli, D., Rooyackers, R., Vandooren, A., Zhuge, J., Kao, K-H., Sorée, B., Magnus, W., Fischetti, M. V., Pourtois, G., Huyghebaert, C., Huang, R., Wang, Y., De Meyer, K., Dehaene, W., Heyns, M. M. & Groeseneken, G., 2011 十二月 1, 69th Device Research Conference, DRC 2011 - Conference Digest. p. 193-196 4 p. 5994494. (Device Research Conference - Conference Digest, DRC).

研究成果: Conference contribution

3 引文 斯高帕斯(Scopus)
2008

Characteristics of PBTI and hot carrier stress for LTPS-TFT with high-κ gate dielectric

Ma, M. W., Chen, C. Y., Su, C. J., Wu, W. C., Wu, Y. H., Kao, K. H., Chao, T. S. & Lei, T. F., 2008 二月 1, 於 : IEEE Electron Device Letters. 29, 2, p. 171-173 3 p.

研究成果: Article

14 引文 斯高帕斯(Scopus)

Fluorinated HfO2 gate dielectrics engineering for CMOS by pre-and post-CF4 plasma passivation

Wu, W. C., Lai, C. S., Lee, S. C., Ming-Wen, M., Chao, T. S., Wang, J. C., Hsu, C. W., Chou, P. C., Chen, J. H., Kao, K. H., Lo, W. C., Lu, T. Y., Tay, L. L. & Rowell, N., 2008 十二月 1, 2008 IEEE International Electron Devices Meeting, IEDM 2008. 4796706. (Technical Digest - International Electron Devices Meeting, IEDM).

研究成果: Conference contribution

8 引文 斯高帕斯(Scopus)

High-performance metal-induced laterally crystallized polycrystalline silicon p-channel thin-film transistor with TaN/HfO2 gate stack structure

Ma, M. W., Chao, T. S., Su, C. J., Wu, W. C., Kao, K. H. & Lei, T. F., 2008 六月 1, 於 : IEEE Electron Device Letters. 29, 6, p. 592-594 3 p.

研究成果: Article

3 引文 斯高帕斯(Scopus)

Impacts of fluorine ion implantation with low-temperature solid-phase crystallized activation on high-κ LTPS-TFT

Ma, M. W., Chen, C. Y., Su, C. J., Wu, W. C., Wu, Y. H., Yang, T. Y., Kao, K. H., Chao, T. S. & Lei, T. F., 2008 二月 1, 於 : IEEE Electron Device Letters. 29, 2, p. 168-170 3 p.

研究成果: Article

6 引文 斯高帕斯(Scopus)

Improvement on performance and reliability of TaN/HfO2 LTPS-TFTs with fluorine implantation

Ma, M. W., Chen, C. Y., Su, C. J., Wu, W. C., Yang, T. Y., Kao, K. H., Chao, T. S. & Lei, T. F., 2008 三月 1, 於 : Solid-State Electronics. 52, 3, p. 342-347 6 p.

研究成果: Article

2 引文 斯高帕斯(Scopus)

Reliability mechanisms of LTPS-TFT with HfO2 gate dielectric: PBTI, NBTI, and hot-carrier stress

Ma, M. W., Chen, C. Y., Wu, W. C., Su, C. J., Kao, K. H., Chao, T. S. & Lei, T. F., 2008 五月 1, 於 : IEEE Transactions on Electron Devices. 55, 5, p. 1153-1160 8 p.

研究成果: Article

34 引文 斯高帕斯(Scopus)

X-ray photoelectron spectroscopy energy band alignment of spin-on CoTiO3 high- k dielectric prepared by sol-gel spin coating method

Kao, K. H., Chuang, S. H., Wu, W. C., Chao, T. S., Chen, J. H., Ma, M. W., Gao, R. H. & Chiang, M. Y., 2008 九月 15, 於 : Applied Physics Letters. 93, 9, 092907.

研究成果: Article

3 引文 斯高帕斯(Scopus)
2007

Impact of High-K Offset Spacer in 65-nm Node SOI Devices

Ma, M. W., Lei, T. F., Wu, C. H., Wang, S. J., Yang, T. Y., Kao, K. H., Wu, W. C. & Chao, T. S., 2007 三月 7, 於 : IEEE Electron Device Letters. 28, 3, p. 238-241 4 p.

研究成果: Article

24 引文 斯高帕斯(Scopus)

Impacts of nitric acid oxidation on low-temperature polycrystalline silicon TFTs with high-κ gate dielectric

Yang, T. Y., Ma, M. W., Kao, K-H., Su, C. J., Chao, T. S. & Lei, T. F., 2007 十二月 1, AD'07 - Proceedings of Asia Display 2007. p. 519-522 4 p. (AD'07 - Proceedings of Asia Display 2007; 卷 1).

研究成果: Conference contribution

Mobility improvement of HfO2 LTPS TFTs with nitrogen implantation

Ma, M. W., Yang, T. Y., Kao, K. H., Su, C. J., Chen, C. Y., Chao, T. S. & Lei, T. F., 2007 十二月 1, AD'07 - Proceedings of Asia Display 2007. p. 674-677 4 p. (AD'07 - Proceedings of Asia Display 2007; 卷 1).

研究成果: Conference contribution

2006
3 引文 斯高帕斯(Scopus)