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查看斯高帕斯 (Scopus) 概要
邱 瀝毅
教授
電機工程學系
https://orcid.org/0000-0002-4161-5787
電話
886 6 2757575 ext 62379
電子郵件
lihyih
mail.ncku.edu
tw
網站
http://www.ee.ncku.edu.tw/subpage_div/teacher_new_2/index2.php?teacher_id=152
h-index
499
引文
10
h-指數
按照存儲在普爾（Pure）的出版物數量及斯高帕斯（Scopus）引文計算。
1994 …
2024
每年研究成果
概覽
指紋
網路
專案
(20)
研究成果
(84)
類似的個人檔案
(6)
監製作品
(19)
指紋
查看啟用 Lih-Yih Chiou 的研究主題。這些主題標籤來自此人的作品。共同形成了獨特的指紋。
排序方式
重量
按字母排序
Engineering
Application Specific Integrated Circuit
19%
Cell Design
19%
Clock Frequency
19%
Code Vector
19%
Complementary Metal-Oxide-Semiconductor
19%
Compression Method
29%
Current Waveform
19%
Data Retention
38%
Design Flow
19%
Design Technique
29%
Dynamic Frequency Scaling
19%
Early Stage
25%
Efficient Implementation
19%
Electric Power Utilization
38%
Electrical Connection
19%
Energy Application
19%
Energy Harvesting
19%
Experimental Result
100%
Flip Flop Circuits
48%
Frequency Domain
19%
Higher-Order Statistics
19%
Image Data
19%
Induced Crosstalk
38%
Input Range
19%
Input Voltage
19%
Integrated Circuit
37%
Level Shifter
19%
Logic Circuit
19%
Low Power Consumption
38%
Major Problem
24%
Matrix Operation
19%
Nonvolatile Memory
27%
Optical Systems
19%
Performance Analysis
58%
Performance Constraint
19%
Point Temperature
19%
Power Management
29%
Priority Level
19%
Process Variation
38%
Random Access Memory
29%
Redundant Bit
19%
Resistive Random Access Memory
19%
Sense Amplifier
60%
Sensing Method
19%
Supply Frequency
19%
Supply Voltage
43%
System-on-Chip
35%
Thermal Sensor
19%
Thermal State
19%
Voltage Scaling
58%
Computer Science
Accelerator Memory
19%
Adaptive Filter Design
38%
Application Specific Integrated Circuit
22%
Clock Skew
19%
Communication Architecture
38%
Computer Hardware
56%
Content-Addressable Memory
19%
Data Access
38%
Digital Signal Processing
19%
Dynamic Power
19%
Embedded System
19%
Energy Consumption
29%
Energy Efficiency
29%
Energy Efficient
87%
Energy Saving
19%
Experimental Result
74%
Field Programmable Gate Array
19%
Graphics Processing Unit
38%
Hardware Architecture
19%
Higher-Order Statistics
19%
Image Classification
19%
Internet-Of-Things
29%
Level Technique
19%
Matrix Multiplication
19%
Matrix Operation
29%
Neural Network Model
19%
Neutral Network
19%
Nonvolatile
53%
Performance Analysis
48%
Power Management
19%
Process Variation
24%
Protection Method
19%
Random Access Memory
22%
Read Only Memory
19%
Search Space
19%
Shifters
19%
Signal Processing Application
19%
Simulated Annealing
19%
Speed-up
19%
Static Random Access Memory
25%
Supernode
19%
Supply Voltage
19%
Switching Activity
19%
System on a Chip
45%
Theoretical Limit
19%
Thermal Profile
19%
Threshold Region
19%
Threshold Voltage
29%
Transmitted Data
19%
Transmitted Signal
19%
Keyphrases
Acoustic Noise Measurement
19%
Adaptive Body Bias
19%
Architecture Exploration
38%
Behavioral Level
19%
Bitline
29%
Bus-based
38%
Code Patterns
19%
Communication Architecture
38%
Content-sensitive
19%
Data Flow Graph
19%
Data Retention Voltage
19%
DSP Applications
19%
Dual Word
19%
Efficient Allocation
19%
Graph Transformation
19%
Heterogeneous CPU-GPU
19%
Higher-order Statistics
19%
Hybrid DRAM-NVM Memories
19%
Intellectual Property
25%
Last-level Cache
19%
Matrix Compression
29%
Memory Content
19%
Minimum Voltage
19%
Multichip Modules
19%
Multimode Systems
19%
Multiple Modes
19%
Near-threshold Voltage
19%
Non-stationary Acoustic Noises
19%
Nonvolatile RAM (NVRAM)
19%
On-a-chip
35%
Performance Constraints
25%
Power Adaptive
19%
Programmable System
19%
Pseudo-parallel
38%
PVT Variations
19%
Redundant Bits
19%
Self-organizing Neural Network
19%
Shielding Method
19%
Single Bitline
19%
Subthreshold Circuit
19%
Synthesis for Low Power
19%
System Level
19%
Thermal Analysis
29%
Thermal Simulator
19%
Variation Tolerance
19%
Weight Detection
19%
Wordline
19%
Write Assist
19%
Write Energy
19%
Write Margin
19%
