Lih-Yih Chiou - 研究成果 - 國立成功大學

查看斯高帕斯 (Scopus) 概要

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每年研究成果

38 Conference contribution
20 Article
16 Patent
5 Conference article
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- 4 Paper
- 1 Editorial

20結果

篩選

2023
Performance Improvement of AlN-Based RRAMs Using Ag Layer for Hardware Security Applications
Min, K. P., Li, C. Y., Wang, T. J., Tsai, C. C., Chu, S. Y. & Chiou, L. Y., 2023 8月 1, 於: IEEE Transactions on Electron Devices. 70, 8, p. 4115-4121 7 p.
研究成果: Article › 同行評審
1 引文斯高帕斯（Scopus）
2021
An Energy-Efficient Conditional Biasing Write Assist with Built-In Time-Based Write-Margin-Tracking for Low-Voltage SRAM
Huang, C. R. & Chiou, L. Y., 2021 8月, 於: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 29, 8, p. 1586-1590 5 p., 9448190.
研究成果: Article › 同行評審
6 引文斯高帕斯（Scopus）
2018
Highly Reliable Two-Step Charge-Pump Read Scheme for 1.5 F²/Bit Nonlinear Sub-Teraohm 0TNR Vertical ReRAM
Chien, T. K., Chiou, L. Y., Chang, C. S., Huang, J. Y., Wu, C. H., Lee, H. Y. & Sheu, S. S., 2018 9月, 於: IEEE Transactions on Circuits and Systems II: Express Briefs. 65, 9, p. 1234-1238 5 p., 8123866.
研究成果: Article › 同行評審
6 引文斯高帕斯（Scopus）
Single bit-line 8T SRAM cell with asynchronous dual word-line control for bitinterleaved ultra-low voltage operation
Huang, C. R. & Chiou, L. Y., 2018 11月 1, 於: IET Circuits, Devices and Systems. 12, 6, p. 713-719 7 p.
研究成果: Article › 同行評審

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8 引文斯高帕斯（Scopus）
Temperature gradient exploration method for determining the appropriate number of cells in mesh-based thermal analysis
Lu, L. Y. & Chiou, L. Y., 2018 12月, 於: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 37, 12, p. 3216-3220 5 p., 8279553.
研究成果: Article › 同行評審
1 引文斯高帕斯（Scopus）
2017
Efficient four-coil wireless power transfer for deep brain stimulation
Yang, C. L., Chang, C. K., Lee, S. Y., Chang, S. J. & Chiou, L. Y., 2017 7月, 於: IEEE Transactions on Microwave Theory and Techniques. 65, 7, p. 2496-2507 12 p., 7896651.
研究成果: Article › 同行評審
68 引文斯高帕斯（Scopus）
Temperature gradient-aware thermal simulator for three-dimensional integrated circuits
Lu, L. Y. & Chiou, L. Y., 2017 9月 1, 於: IET Computers and Digital Techniques. 11, 5, p. 190-196 7 p.
研究成果: Article › 同行評審
7 引文斯高帕斯（Scopus）
2016
Low-Power MCU with Embedded ReRAM Buffers as Sensor Hub for IoT Applications
Chien, T. K., Chiou, L. Y., Sheu, S. S., Lin, J. C., Lee, C. C., Ku, T. K., Tsai, M. J. & Wu, C. I., 2016 6月, 於: IEEE Journal on Emerging and Selected Topics in Circuits and Systems. 6, 2, p. 247-257 11 p., 7453196.
研究成果: Article › 同行評審
35 引文斯高帕斯（Scopus）
2010
A sub-200-mV voltage-scalable SRAM with tolerance of access failure by self-activated bitline sensing
Luo, S. C. & Chiou, L. Y., 2010 6月, 於: IEEE Transactions on Circuits and Systems II: Express Briefs. 57, 6, p. 440-445 6 p., 5471175.
研究成果: Article › 同行評審
14 引文斯高帕斯（Scopus）
Energy-efficient hardware architecture and VLSI implementation of a polyphase channelizer with applications to subband adaptive filtering
Wang, Y., Mahmoodi, H., Chiou, L. Y., Choo, H., Park, J., Jeong, W. & Roy, K., 2010 2月, 於: Journal of Signal Processing Systems. 58, 2, p. 125-137 13 p.
研究成果: Article › 同行評審
9 引文斯高帕斯（Scopus）
2009
Energy-efficient dual-edge-triggered level converting flip flops with symmetry in setup times and insensitivity to output parasitics
Chiou, L. Y. & Luo, S. C., 2009 11月, 於: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 17, 11, p. 1659-1663 5 p., 4814496.
研究成果: Article › 同行評審
2 引文斯高帕斯（Scopus）
System-level bus-based communication architecture exploration using a pseudoparallel algorithm
Chiou, L. Y., Chen, Y. S. & Lee, C. H., 2009 8月, 於: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 28, 8, p. 1213-1223 11 p., 5166607.
研究成果: Article › 同行評審
1 引文斯高帕斯（Scopus）
System-level bus-based communication architecture exploration using a pseudoparallel algorithm
Chiou, L. Y., Chen, Y. S. & Lee, C. H., 2009 1月 1, 於: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 28, 1, p. 1213-1223 11 p.
研究成果: Article › 同行評審
1 引文斯高帕斯（Scopus）
2006
A full code-patterns coverage high-speed embedded ROM using dynamic virtual guardian technique
Chang, M. F., Chiou, L. Y. & Wen, K. A., 2006 2月, 於: IEEE Journal of Solid-State Circuits. 41, 2, p. 496-506 11 p.
研究成果: Article › 同行評審
14 引文斯高帕斯（Scopus）
Crosstalk-Insensitive Via-Programming ROMs Using Content-Aware Design Framework
Chang, M. F., Chiou, L. Y. & Wen, K. A., 2006, 於: IEEE Transactions on Circuits and Systems II: Express Briefs. 53, 6, p. 443-447 5 p.
研究成果: Article › 同行評審
8 引文斯高帕斯（Scopus）
2005
Code-pattern insensitive embedded ROMs using dynamic bitline shielding technique
Chang, M. F., Chiou, L. Y. & Wen, K. A., 2005 7月 21, 於: Electronics Letters. 41, 15, p. 834-835 2 p.
研究成果: Article › 同行評審
1 引文斯高帕斯（Scopus）
Synthesis of Application-Specific Highly Efficient Multi-Mode Cores for Embedded Systems
Chiou, L. Y., Bhunia, S. & Roy, K., 2005 2月 1, 於: ACM Transactions on Embedded Computing Systems. 4, 1, p. 168-188 21 p.
研究成果: Article › 同行評審
20 引文斯高帕斯（Scopus）
2002
Leakage control with efficient use of transistor stacks in single threshold CMOS
Johnson, M. C., Somasekhar, D., Chiou, L. Y. & Roy, K., 2002 2月, 於: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 10, 1, p. 1-5 5 p.
研究成果: Article › 同行評審
140 引文斯高帕斯（Scopus）
2001
Signal strength based switching activity modeling and estimation for DSP applications
Chiou, L. Y., Muhammand, K. & Roy, K., 2001, 於: VLSI Design. 12, 2, p. 233-243 11 p.
研究成果: Article › 同行評審

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3 引文斯高帕斯（Scopus）
2000
Concentrator circuit with multiple priority levels
Krishnamoorthy, A. V., Chiou, L. Y., Rozier, R. G. & Kibar, O., 2000 3月 16, 於: Electronics Letters. 36, 6, p. 500-501 2 p.
研究成果: Article › 同行評審