每年專案
個人檔案
學歷
- 2001 佛羅里達大學電機暨電腦工程博士
研究專長
- 模型與模擬
- 半導體元件物理
經歷
- 2001~2003 AMD資深元件工程師
- 2003年2月 ~ 2014年1月 國立宜蘭大學電子工程學系助理教授/副教授/教授
- 2014年2月 ~ 2015年7月 國立成功大學電機工程學系副教授
- 2015年08月~ 迄今國立成功大學電機工程學系教授
指紋
查看啟用 Meng-Hsueh Chiang 的研究主題。這些主題標籤來自此人的作品。共同形成了獨特的指紋。
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過去五年中的合作和熱門研究領域
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專案
- 5 已完成
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First Demonstration of Defect Elimination for Cryogenic Ge FinFET CMOS Inverter Showing Steep Subthreshold Slope by Using Ge-on-Insulator Structure
Yu, X. R., Hsieh, C. C., Chuang, M. H., Chiu, M. Y., Sun, T. C., Geng, W. Z., Chang, W. H., Shih, Y. J., Lu, W. H., Chang, W. C., Lin, Y. C., Pai, Y. C., Lai, C. Y., Chuang, M. H., Dei, Y., Yang, C. Y., Lu, H. Y., Lin, N. C., Wu, C. T., Kao, K. H., 及其他9 , 2023, 2023 International Electron Devices Meeting, IEDM 2023. Institute of Electrical and Electronics Engineers Inc., (Technical Digest - International Electron Devices Meeting, IEDM).研究成果: Conference contribution
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How Fault-Tolerant Quantum Computing Benefits from Cryo-CMOS Technology
Chiang, H. L., Hadi, R. A., Wang, J. F., Han, H. C., Wu, J. J., Hsieh, H. H., Horng, J. J., Chou, W. S., Lien, B. S., Chang, C. H., Chen, Y. C., Wang, Y. H., Chen, T. C., Liu, J. C., Liu, Y. C., Chiang, M. H., Kao, K. H., Pulicherla, B., Cai, J., Chang, C. S., 及其他9 , 2023, 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023. Institute of Electrical and Electronics Engineers Inc., (Digest of Technical Papers - Symposium on VLSI Technology; 卷 2023-June).研究成果: Conference contribution
3 引文 斯高帕斯(Scopus) -
Modeling of Bilayer Modulated RRAM and Its Array Performance for Compute-in-Memory Applications
Lee, J. W., Chou, T. C., Chen, P. A. & Chiang, M. H., 2023 12月 1, 於: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits. 9, 2, p. 151-158 8 p.研究成果: Article › 同行評審
開啟存取3 引文 斯高帕斯(Scopus) -
MOSFET Characterization with Reduced Supply Voltage at Low Temperatures for Power Efficiency Maximization
Lin, W. C., Huang, H. P., Kao, K. H., Chiang, M. H., Lu, D., Hsu, W. C., Wang, Y. H., Ma, W. C. Y., Tsai, H. H., Lee, Y. J., Chiang, H. L., Wang, J. F. & Radu, I., 2023, ESSDERC 2023 - IEEE 53rd European Solid-State Device Research Conference. Editions Frontieres, p. 9-12 4 p. (European Solid-State Device Research Conference; 卷 2023-September).研究成果: Conference contribution
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Performance Comparison of SRAM Designs Implemented with Silicon-On-Insulator Nanosheet Transistors and Bulk FinFETs
Chen, P. C., Wu, Y. T. & Chiang, M. H., 2023, ESSDERC 2023 - IEEE 53rd European Solid-State Device Research Conference. Editions Frontieres, p. 73-76 4 p. (European Solid-State Device Research Conference; 卷 2023-September).研究成果: Conference contribution