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個人檔案

學歷

  • 2001 佛羅里達大學電機暨電腦工程博士

研究專長

  • 模型與模擬
  • 半導體元件物理

經歷

  • 2001~2003 AMD資深元件工程師
  • 2003年2月 ~ 2014年1月 國立宜蘭大學電子工程學系助理教授/副教授/教授
  • 2014年2月 ~ 2015年7月 國立成功大學電機工程學系副教授
  • 2015年08月~ 迄今國立成功大學電機工程學系教授

指紋 查看啟用 Meng-Hsueh Chiang 的研究主題。這些主題標籤來自此人的作品。共同形成了獨特的指紋。

  • 2 類似的檔案
Nanowires Engineering & Materials Science
Static random access storage Engineering & Materials Science
Phase change memory Engineering & Materials Science
Field effect transistors Engineering & Materials Science
Transistors Engineering & Materials Science
Doping (additives) Engineering & Materials Science
Silicon Engineering & Materials Science
High electron mobility transistors Engineering & Materials Science

網絡 國家層面的近期外部合作。點選圓點深入探索詳細資料。

研究計畫 2016 2018

研究成果 1998 2019

  • 694 引文
  • 12 h-指數
  • 46 Conference contribution
  • 37 Article
  • 3 Conference article
  • 2 Paper

An RRAM with a 2D material embedded double switching layer for neuromorphic computing

Chen, P. A., Ge, R. J., Lee, J. W., Hsu, C. H., Hsu, W-C., Akinwande, D. & Chiang, M-H., 2019 一月 8, 2018 IEEE 13th Nanotechnology Materials and Devices Conference, NMDC 2018. Institute of Electrical and Electronics Engineers Inc., 8605915. (2018 IEEE 13th Nanotechnology Materials and Devices Conference, NMDC 2018).

研究成果: Conference contribution

random access memory
oxygen ions
plastic properties
Plasticity
Ions

Atomristors: Memory Effect in Atomically-thin Sheets and Record RF Switches

Ge, R., Wu, X., Kim, M., Chen, P. A., Shi, J., Choi, J., Li, X., Zhang, Y., Chiang, M-H., Lee, J. C. & Akinwande, D., 2019 一月 16, 2018 IEEE International Electron Devices Meeting, IEDM 2018. Institute of Electrical and Electronics Engineers Inc., p. 22.6.1-22.6.4 8614602. (Technical Digest - International Electron Devices Meeting, IEDM; 卷 2018-December).

研究成果: Conference contribution

switches
Switches
Data storage equipment
Monolayers
Sulfur

Insights to the scaling impact on back-gate biasing for FD SOI MOSFETs

Chang, M. Y., Wang, L. J. & Chiang, M-H., 2019 二月 11, 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018. Institute of Electrical and Electronics Engineers Inc., 8640185. (2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018).

研究成果: Conference contribution

SOI (semiconductors)
field effect transistors
thin bodies
inversions
scaling

Simulation-based study of high-density SRAM voltage scaling enabled by inserted-oxide FinFET technology

Wu, Y. T., Ding, F., Connelly, D., Chiang, M-H., Chen, J-F. & Liu, T. J. K., 2019 四月 1, 於 : IEEE Transactions on Electron Devices. 66, 4, p. 1754-1759 6 p., 8661752.

研究成果: Article

Static random access storage
Oxides
Nanowires
Transistors
Electric potential
1 引文 (Scopus)

Speed Optimization of Vertically Stacked Gate-All-Around MOSFETs with Inner Spacers for Low Power and Ultra-Low Power Applications

Huang, Y. C., Chiang, M-H. & Wang, S-J., 2019 四月 23, Proceedings of the 20th International Symposium on Quality Electronic Design, ISQED 2019. IEEE Computer Society, p. 231-234 4 p. 8697706. (Proceedings - International Symposium on Quality Electronic Design, ISQED; 卷 2019-March).

研究成果: Conference contribution

Controllability
Leakage currents
Masks
Capacitance
Tuning

論文

Analysis of the Multi-Vt FD-SOI MOSFETs and SRAM Application

作者: 政邑, 陳., 2018 一月 16

監督員: Chiang, M. (Supervisor)

學生論文: Master's Thesis

Characterization and Analysis of Oxide Interface Charge for FinFETs

作者: 如諒, 賴., 2017 六月 21

監督員: Chiang, M. (Supervisor)

學生論文: Master's Thesis

Characterization and Modeling of Via Resistance for FinFETs

作者: 博任, 楊., 2018 二月 7

監督員: Chiang, M. (Supervisor)

學生論文: Master's Thesis

Modeling of IGZO Thin-Film Transistors for Circuit Simulations

作者: 欣翰, 李., 2018 六月 26

監督員: Chiang, M. (Supervisor)

學生論文: Master's Thesis

Performance Optimization of Gate-All-Around MOSFETs by Inner Spacers at 5 nm Technology Node

作者: 仕豪, 陳., 2018 二月 7

監督員: Chiang, M. (Supervisor)

學生論文: Master's Thesis