• 811 引文
  • 15 h-指數
1992 …2020

每年研究成果

如果您對這些純文本內容做了任何改變,很快就會看到。

研究成果

篩選
Paper
2012

Efficient scissoring scheme for scanline-based rendering of 2D vector graphics

Lin, W. C., Ye, J. H., Yang, D. W., Huang, S. Y., Shieh, M-D. & Wang, J., 2012 九月 28, p. 766-769. 4 p.

研究成果: Paper

1 引文 斯高帕斯(Scopus)

Fast scalable radix-4 Montgomery modular multiplier

Wang, S. H., Lin, W. C., Ye, J. H. & Shieh, M-D., 2012 九月 28, p. 3049-3052. 4 p.

研究成果: Paper

22 引文 斯高帕斯(Scopus)
2004
2 引文 斯高帕斯(Scopus)

High-speed VLSI design for montgomery inverse over GF(2 m)

Chen, J. H., Shieh, M. D. & Wu, C. M., 2004 十二月 1, p. 25-28. 4 p.

研究成果: Paper

1 引文 斯高帕斯(Scopus)
1997

A versatile signal processing board for real-time multimedia communication

Wang, M. R., Wang, J. S., Huang, Y. T., Hsu, M. H., Shieh, M-D., Wu, C. H. & Jeng, B. S., 1997 十二月 1, p. 331-334. 4 p.

研究成果: Paper

Dichotomy-based constrained encoding for low switching activity in asynchronous finite state machines

Shieh, M-D., Sheu, M. H., Wang, H. R. & Cheng, H. C., 1997 十二月 1, p. 509-512. 4 p.

研究成果: Paper

Efficient hardware design approach from system-level specification

Sheu, M. H., Shieh, M-D., Liu, S. W. & Dou, C., 1997 十二月 1, p. 1213-1216. 4 p.

研究成果: Paper

Low-cost VLSI architecture design for non-separable 2-D Discrete Wavelet Transform

Sheu, M. H., Shieh, M-D. & Liu, S. W., 1997 十二月 1, p. 1217-1220. 4 p.

研究成果: Paper

4 引文 斯高帕斯(Scopus)

Low-power VLSI architecture for the Viterbi decoder

Ju, W. S., Shieh, M. D. & Sheu, M. H., 1997 十二月 1, p. 1201-1204. 4 p.

研究成果: Paper

2 引文 斯高帕斯(Scopus)

On the implementation of wave-pipelined multipliers in lookup table-based FPGAs

Ke, Y. S., Shieh, M-D. & Sheu, M. H., 1997 十二月 1, p. 434-437. 4 p.

研究成果: Paper

1996

MAPS: A new and efficient block-matching criterion for motion estimation

Shieh, M. D., Sheu, M. H. & Hsu, Y. C., 1996 十二月 1, p. 1393-1396. 4 p.

研究成果: Paper