每年研究計畫
個人檔案
學歷
- 2002 國立交通大學電子研究所博士
研究專長
- 電腦輔助積體電路設計
- 混合信號積體電路設計、測試與可測試設計
經歷
- 2002年10月~2003年1月 工研院系統晶片中心工程師
- 2003年2月~2008年7月 國立成功大學電機系助理教授
- 2008年8月~2011年7月 國立成功大學電機系副教授
- 2009年1月~2012年12月 國際電機電子工程師學會 固態電路學會台南支會主席
- 2011年8月~2014年7月 國立成功大學電機工廠主任
- 2011年8月~迄今 國立成功大學電機系教授
指紋 查看啟用 Soon-Jyh Chang 的研究主題。這些主題標籤來自此人的作品。共同形成了獨特的指紋。
- 7 類似的檔案
Digital to analog conversion
Engineering & Materials Science
Networks (circuits)
Engineering & Materials Science
Capacitors
Engineering & Materials Science
Operational amplifiers
Engineering & Materials Science
Electric power utilization
Engineering & Materials Science
Built-in self test
Engineering & Materials Science
Electric potential
Engineering & Materials Science
Clock and data recovery circuits (CDR circuits)
Engineering & Materials Science
網絡
國家層面的近期外部合作。點選圓點深入探索詳細資料。
研究計畫 2003 2020
具高安全性且低耗能之物聯網晶片電路及系統之分析、設計及實作-子計畫三：應用於高安全性且低耗能物聯網系統的類比至數位轉換器之研製(2/2)
19-05-01 → 20-04-30
研究計畫: Research project
考量三維晶片平面規畫與除錯之低功耗動態調整電壓與頻率之設計方法-子計畫三：應用於三維晶片之溫度感測與時脈電路設計技術研發
15-08-01 → 16-07-31
研究計畫: Research project
研究成果 1997 2019
A 10-bit 1-GS/s 2x-interleaved timing-skew calibration free SAR ADC
Hu, H. J., Cheng, Y. S. & Chang, S-J., 2019 一月 1, 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 8702455. (Proceedings - IEEE International Symposium on Circuits and Systems; 卷 2019-May).研究成果: Conference contribution
Digital to analog conversion
Calibration
Clocks
Switches
Networks (circuits)
A 2-GS/s 8b flash-SAR time-interleaved ADC with background offset calibration
Cheng, Y. S., Hu, H. J. & Chang, S-J., 2019 一月 1, 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 8702543. (Proceedings - IEEE International Symposium on Circuits and Systems; 卷 2019-May).研究成果: Conference contribution
Calibration
Networks (circuits)
Redundancy
Clocks
A 11-bit 35-MS/s wide input range SAR ADC in 180-nm CMOS process
Luo, W. C., Chang, S-J., Huang, C. P. & Wu, H. S., 2018 六月 5, 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018. Institute of Electrical and Electronics Engineers Inc., p. 1-4 4 p. (2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018).研究成果: Conference contribution
Analog-to-digital Converter
Successive Approximation
Digital to analog conversion
Range of data
Networks (circuits)
2
引文
(Scopus)
A 12-b 40-MS/s Calibration-Free SAR ADC
Hsu, C. W., Chang, S-J., Huang, C. P., Chang, L. J., Shyu, Y. T., Hou, C. H., Tseng, H. A., Kung, C. Y. & Hu, H. J., 2018 三月 1, 於 : IEEE Transactions on Circuits and Systems I: Regular Papers. 65, 3, p. 881-890 10 p.研究成果: Article
Digital to analog conversion
Calibration
Capacitors
Sampling
Networks (circuits)
A Fast and Jitter-Modulation Free Jitter Tolerance Estimation Technique for Bang-Bang CDRs
Lee, Y. L., Cheng, Y. P., Chang, S-J. & Ting, H. W., 2018 二月 1, 於 : IEEE Design and Test. 35, 1, p. 63-73 11 p., 8039277.研究成果: Article
Clock and data recovery circuits (CDR circuits)
Jitter
Modulation
論文
A 0 5-to-3 0 Gb/s Dual Edge Sampling Delay-Locked Loop Based Clock and Data Recovery Circuit
Author: 繼仁, 吳., 2014 八月 20Supervisor: Chang, S. (Supervisor)
Student thesis: Master's Thesis
A 0 5-to-5 Gbps Continuous Rate Clock and Data Recovery Circuit with Bi-directional Frequency Detection
Author: 彥錡, 陳., 2014 三月 7Supervisor: Chang, S. (Supervisor)
Student thesis: Master's Thesis
A 10-bit 120-MS/s SAR ADC with Compact Architecture and Noise Suppression Technique
Author: 哲勳, 郭., 2014 八月 22Supervisor: Chang, S. (Supervisor)
Student thesis: Master's Thesis
A 10-bit 300-MS/s Successive-Approximation Analog-to-Digital Converter with a Pre-amplifier-only Comparator
Author: 恩澤, 寸., 2019Supervisor: Chang, S. (Supervisor)
Student thesis: Master's Thesis
A 10-bit 600-MS/s 2x-Interleaved Timing-Skew Insensitive Successive-Approximation Analog-to-Digital Converter
Author: 桓睿, 胡., 2019Supervisor: Chang, S. (Supervisor)
Student thesis: Master's Thesis