Soon-Jyh Chang

2020

A 14-bit low power 2-ms/s sar adc with residue oversampling*

Huang, S. W., Chang, L. J. & Chang, S. J., 2020 6月, 於: International Journal of Electrical Engineering. 27, 3, p. 105-114 10 p.

研究成果: Article › 同行評審

Detection System for Capacitive Plantar Pressure Monitoring

Tsai, T. M., Lee, S. Y. & Chang, S. J., 2020, 於: IEEE Access. 8, p. 42633-42655 23 p., 9016197.

研究成果: Article › 同行評審

開啟存取

6 引文斯高帕斯（Scopus）

Monitoring System with Cross-Type Capacitive Plantar Pressure Sensor

Tsai, T. M., Tsou, C., Huang, P. W., Lee, S. Y. & Chang, S. J., 2020 10月 1, 於: IEEE Sensors Journal. 20, 19, p. 11138-11155 18 p., 9096334.

研究成果: Article › 同行評審

5 引文斯高帕斯（Scopus）

2018

A 12-b 40-MS/s Calibration-Free SAR ADC

Hsu, C. W., Chang, S. J., Huang, C. P., Chang, L. J., Shyu, Y. T., Hou, C. H., Tseng, H. A., Kung, C. Y. & Hu, H. J., 2018 3月, 於: IEEE Transactions on Circuits and Systems I: Regular Papers. 65, 3, p. 881-890 10 p.

研究成果: Article › 同行評審

22 引文斯高帕斯（Scopus）

A Fast and Jitter-Modulation Free Jitter Tolerance Estimation Technique for Bang-Bang CDRs

Lee, Y. L., Cheng, Y. P., Chang, S. J. & Ting, H. W., 2018 2月, 於: IEEE Design and Test. 35, 1, p. 63-73 11 p., 8039277.

研究成果: Article › 同行評審

2017

Analyses of Splittable Amplifier Technique and Cancellation of Memory Effect for Opamp Sharing

Chao, I. J., Liu, B. D., Chang, S. J., Huang, C. Y. & Ting, H. W., 2017 2月, 於: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 25, 2, p. 621-634 14 p., 7517306.

研究成果: Article › 同行評審

1 引文斯高帕斯（Scopus）

An Unbounded Frequency Detection Mechanism for Continuous-Rate CDR Circuits

Lee, Y. L., Chang, S. J., Chen, Y. C. & Cheng, Y. P., 2017 5月, 於: IEEE Transactions on Circuits and Systems II: Express Briefs. 64, 5, p. 500-504 5 p., 7498576.

研究成果: Article › 同行評審

12 引文斯高帕斯（Scopus）

Efficient four-coil wireless power transfer for deep brain stimulation

Yang, C. L., Chang, C. K., Lee, S. Y., Chang, S. J. & Chiou, L. Y., 2017 7月, 於: IEEE Transactions on Microwave Theory and Techniques. 65, 7, p. 2496-2507 12 p., 7896651.

研究成果: Article › 同行評審

56 引文斯高帕斯（Scopus）

2016

Analysis of Nonideal Behaviors Based on INL/DNL Plots for SAR ADCs

Huang, C. P., Ting, H. W. & Chang, S. J., 2016 8月, 於: IEEE Transactions on Instrumentation and Measurement. 65, 8, p. 1804-1817 14 p., 7470271.

研究成果: Article › 同行評審

19 引文斯高帕斯（Scopus）

An Efficient and Effective Methodology to Control Turn-On Sequence of Power Switches for Power Gating Designs

Shyu, Y. T., Lin, J. M., Lin, C. C., Huang, C. P. & Chang, S. J., 2016 10月, 於: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 35, 10, p. 1730-1743 14 p., 7401015.

研究成果: Article › 同行評審

2 引文斯高帕斯（Scopus）

A Systematic Design Methodology of Asynchronous SAR ADCs

Huang, C. P., Lin, J. M., Shyu, Y. T. & Chang, S. J., 2016 5月, 於: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 24, 5, p. 1835-1848 14 p., 7332786.

研究成果: Article › 同行評審

19 引文斯高帕斯（Scopus）

2015

A capacitance-ratio quantification design for linearity test in differential top-plate sampling sar ADCS

Chao, A. S., Lin, C. W., Ting, H. W. & Chang, S. J., 2015 10月, 於: International Journal of Circuit Theory and Applications. 43, 10, p. 1333-1350 18 p.

研究成果: Article › 同行評審

1 引文斯高帕斯（Scopus）

2014

A 0.5-TO-4 GBPS continuous-rate clock and data recovery circuit with bidirectional frequency detection

Lee, Y. L., Chen, Y. C., Chang, S. J. & Cheng, Y. P., 2014 12月 1, 於: International Journal of Electrical Engineering. 21, 6, p. 243-252 10 p.

研究成果: Article › 同行評審

1 引文斯高帕斯（Scopus）

A low-cost stimulus design for linearity test in SAR ADCs

Chao, A. S., Lin, C. W., Ting, H. W. & Chang, S. J., 2014 6月, 於: IEICE Transactions on Electronics. E97-C, 6, p. 538-545 8 p.

研究成果: Article › 同行評審

1 引文斯高帕斯（Scopus）

A primary-auxiliary temperature sensing scheme for multiple hotspots in system-on-a-chips

Chen, P. Y., Huang, G. Y., Shyu, Y. T. & Chang, S. J., 2014 8月, 於: IEEE Sensors Journal. 14, 8, p. 2633-2642 10 p., 6781600.

研究成果: Article › 同行評審

5 引文斯高帕斯（Scopus）

A single opamp third-order low-distortion delta-sigma modulator with SAR quantizer embedded passive adder

Chao, I. J., Hou, C. W., Liu, B. D., Chang, S. J. & Huang, C. Y., 2014 6月, 於: IEICE Transactions on Electronics. E97-C, 6, p. 526-537 12 p.

研究成果: Article › 同行評審

9 引文斯高帕斯（Scopus）

2013

10-bit 30-MS/s SAR ADC using a switchback switching method

Huang, G. Y., Chang, S. J., Liu, C. C. & Lin, Y. Z., 2013, 於: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 21, 3, p. 584-588 5 p., 6172687.

研究成果: Article › 同行評審

84 引文斯高帕斯（Scopus）

A 9-bit 150-MS/s subrange ADC based on SAR architecture in 90-nm CMOS

Lin, Y. Z., Liu, C. C., Huang, G. Y., Shyu, Y. T., Liu, Y. T. & Chang, S. J., 2013, 於: IEEE Transactions on Circuits and Systems I: Regular Papers. 60, 3, p. 570-581 12 p., 6459552.

研究成果: Article › 同行評審

64 引文斯高帕斯（Scopus）

Effective and efficient approach for power reduction by using multi-bit flip-flops

Shyu, Y. T., Lin, J. M., Huang, C. P., Lin, C. W., Lin, Y. Z. & Chang, S. J., 2013, 於: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 21, 4, p. 624-635 12 p., 6178020.

研究成果: Article › 同行評審

49 引文斯高帕斯（Scopus）

2012

A 1-μW 10-bit 200-kS/s SAR ADC with a bypass window for biomedical applications

Huang, G. Y., Chang, S. J., Liu, C. C. & Lin, Y. Z., 2012, 於: IEEE Journal of Solid-State Circuits. 47, 11, p. 2783-2795 13 p., 6339066.

研究成果: Article › 同行評審

123 引文斯高帕斯（Scopus）

A 6-bit current-steering DAC with compound current cells for both communication and rail-to-rail voltage-source applications

Chen, R. L. & Chang, S. J., 2012, 於: IEEE Transactions on Circuits and Systems II: Express Briefs. 59, 11, p. 746-750 5 p., 6341058.

研究成果: Article › 同行評審

14 引文斯高帕斯（Scopus）

A low-cost bit-error-rate BIST circuit for high-speed ADCs based on gray coding

Shyu, Y. T., Lin, Y. Z., Chu, R. S., Huang, G. Y. & Chang, S. J., 2012 12月, 於: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E95-A, 12, p. 2415-2423 9 p.

研究成果: Article › 同行評審

A third-order low-distortion delta-sigma modulator with opamp sharing and relaxed feedback path timing

Chao, I. J., Hsu, C. L., Liu, B. D., Chang, S. J., Huang, C. Y. & Ting, H. W., 2012 11月, 於: IEICE Transactions on Electronics. E95-C, 11, p. 1799-1809 11 p.

研究成果: Article › 同行評審

3 引文斯高帕斯（Scopus）

Mismatch-aware common-centroid placement for arbitrary-ratio capacitor arrays considering dummy capacitors

Lin, C. W., Lin, J. M., Chiu, Y. C., Huang, C. P. & Chang, S. J., 2012, 於: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 31, 12, p. 1789-1802 14 p., 6349434.

研究成果: Article › 同行評審

31 引文斯高帕斯（Scopus）

Six-bit 2.7-GS/s 5.4-mW Nyquist complementary metal-oxide semiconductor digital-to-analogue converter for ultra-wideband transceivers

Chen, R. L., Ting, H. W. & Chang, S. J., 2012 3月, 於: IET Circuits, Devices and Systems. 6, 2, p. 95-102 8 p.

研究成果: Article › 同行評審

6 引文斯高帕斯（Scopus）

2011

A design of linearity built-in self-test for current-steering DAC

Ting, H. W., Chang, S. J. & Huang, S. L., 2011 2月, 於: Journal of Electronic Testing: Theory and Applications (JETTA). 27, 1, p. 85-94 10 p.

研究成果: Article › 同行評審

13 引文斯高帕斯（Scopus）

A low-power mixed-architecture adc with time-interleaved correlated double sampling technique and power-efficient back-end stages

Lin, J. F. & Chang, S. J., 2011 1月, 於: IEICE Transactions on Electronics. E94-C, 1, p. 89-101 13 p.

研究成果: Article › 同行評審

1 引文斯高帕斯（Scopus）

Transition-code based linearity test method for pipelined ADCs with digital error correction

Lin, J. F., Chang, S. J., Kung, T. C., Ting, H. W. & Huang, C. H., 2011 12月, 於: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 19, 12, p. 2158-2169 12 p., 5648403.

研究成果: Article › 同行評審

22 引文斯高帕斯（Scopus）

2010

A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure

Liu, C. C., Chang, S. J., Huang, G. Y. & Lin, Y. Z., 2010 4月, 於: IEEE Journal of Solid-State Circuits. 45, 4, p. 731-740 10 p., 5437496.

研究成果: Article › 同行評審

967 引文斯高帕斯（Scopus）

A 10-bit 60-MS/s low-power pipelined ADC with split-capacitor CDS technique

Lin, J. F., Chang, S. J., Liu, C. C. & Huang, C. H., 2010 3月, 於: IEEE Transactions on Circuits and Systems II: Express Briefs. 57, 3, p. 163-167 5 p., 5431013.

研究成果: Article › 同行評審

24 引文斯高帕斯（Scopus）

A 5-bit 3.2-GS/s flash ADC with a digital offset calibration scheme

Lin, Y. Z., Lin, C. W. & Chang, S. J., 2010 3月, 於: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 18, 3, p. 509-513 5 p., 5034721.

研究成果: Article › 同行評審

35 引文斯高帕斯（Scopus）

An asynchronous binary-search ADC architecture with a reduced comparator count

Lin, Y. Z., Chang, S. J., Liu, Y. T., Liu, C. C. & Huang, G. Y., 2010, 於: IEEE Transactions on Circuits and Systems I: Regular Papers. 57, 8, p. 1829-1837 9 p., 5378479.

研究成果: Article › 同行評審

47 引文斯高帕斯（Scopus）

2009

A 5-bit 4.2-GS/s flash ADC in 0.13-μm CMOS process

Lin, Y. Z., Chang, S. J. & Liu, Y. T., 2009 1月 1, 於: IEICE Transactions on Electronics. E92-C, 2, p. 258-268 11 p.

研究成果: Article › 同行評審

3 引文斯高帕斯（Scopus）

Low-power and wide-bandwidth cyclic ADC with capacitor and opamp reuse techniques for CMOS image sensor application

Lin, J. F., Chang, S. J., Chiu, C. F., Tsai, H. H. & Wang, J. J., 2009, 於: IEEE Sensors Journal. 9, 12, p. 2044-2054 11 p., 05310989.

研究成果: Article › 同行評審

17 引文斯高帕斯（Scopus）

2008

A 0.8-V 250-MSample/s double-sampled inverse-flip-around sample-and-hold circuit based on switched-opamp architecture

Ou, H. H., Liu, B. D. & Chang, S. J., 2008 9月, 於: IEICE Transactions on Electronics. E91-C, 9, p. 1480-1487 8 p.

研究成果: Article › 同行評審

3 引文斯高帕斯（Scopus）

A digitally calibrated CMOS transconductor with a 100-MHz bandwidth and 75-dB SFDR

Chang, S. J., Lin, Y. Z. & Liu, Y. T., 2008, 於: IEEE Transactions on Circuits and Systems II: Express Briefs. 55, 11, p. 1089-1093 5 p.

研究成果: Article › 同行評審

8 引文斯高帕斯（Scopus）

A histogram-based testing method for estimating A/D converter performance

Ting, H. W., Liu, B. D. & Chang, S. J., 2008 2月, 於: IEEE Transactions on Instrumentation and Measurement. 57, 2, p. 420-427 8 p.

研究成果: Article › 同行評審

42 引文斯高帕斯（Scopus）

A versatile step-up/step-down switched-capacitor-based DC-DC converter

Wei, C. L., Wu, L. Y., Yang, H. H., Tsai, C. H., Liu, B. D. & Chang, S. J., 2008 5月, 於: IEICE Transactions on Electronics. E91-C, 5, p. 809-812 4 p.

研究成果: Article › 同行評審

24 引文斯高帕斯（Scopus）

Low-power circuit techniques for low-voltage pipelined ADCs based on switched-opamp architecture

Ou, H. H., Chang, S. J. & Liu, B. D., 2008, 於: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E91-A, 2, p. 461-468 8 p.

研究成果: Article › 同行評審

3 引文斯高帕斯（Scopus）

2007

Oscillator-based reconfigurable sinusoidal signal generator for ADC BIST

Ting, H. W., Lin, C. W., Liu, B. D. & Chang, S. J., 2007 12月, 於: Journal of Electronic Testing: Theory and Applications (JETTA). 23, 6, p. 549-558 10 p.

研究成果: Article › 同行評審

3 引文斯高帕斯（Scopus）

2004

A time domain built-in self-test methodology for SNDR and ENOB tests of analog-to-digital converters

Ting, H. W., Liu, B-D. & Chang, S-J., 2004, 於: Proceedings of the Asian Test Symposium. p. 52-57 6 p.

研究成果: Article › 同行評審

4 引文斯高帕斯（Scopus）

2003

Structure-based specification-constrained test frequency generation for linear analog circuits

Chang, S-J., Lee, C. L. & Chen, J. E., 2003 7月 1, 於: Journal of Information Science and Engineering. 19, 4, p. 637-651 15 p.

研究成果: Article › 同行評審

2002

BIST scheme for DAC testing

Chang, S-J., Lee, C. L. & Chen, J. E., 2002 7月 18, 於: Electronics Letters. 38, 15, p. 776-777 2 p.

研究成果: Article › 同行評審

23 引文斯高帕斯（Scopus）

Structural fault based specification reduction for testing analog circuits

Chang, S. J., Lee, C. L. & Chen, J. E., 2002 12月, 於: Journal of Electronic Testing: Theory and Applications (JETTA). 18, 6, p. 571-581 11 p.

研究成果: Article › 同行評審

8 引文斯高帕斯（Scopus）

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