每年研究成果
每年研究成果
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搜尋結果
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2024
Modelling individual differences in reading using an optimised MikeNet simulator: the impact of reading instruction
Ya-Ning, C., Chang, T. J., Lin, W. F., Kuo, C. E., Shi, Y. T. & Lee, H. W., 2024, 於: Frontiers in Human Neuroscience. 18, 1356483.研究成果: Article › 同行評審
開啟存取 -
2019
ONNC: A Compilation Framework Connecting ONNX to Proprietary Deep Learning Accelerators
Lin, W. F., Tsai, D. Y., Tang, L., Hsieh, C. T., Chou, C. Y., Chang, P. H. & Hsu, L., 2019 3月, Proceedings 2019 IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2019. Institute of Electrical and Electronics Engineers Inc., p. 214-218 5 p. 8771510. (Proceedings 2019 IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2019).研究成果: Conference contribution
44 引文 斯高帕斯（Scopus） -
ONNC-based software development platform for configurable NVDLA designs
Lin, W. F., Hsieh, C. T. & Chou, C. Y., 2019 4月, 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019. Institute of Electrical and Electronics Engineers Inc., 8741778. (2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019).研究成果: Conference contribution
4 引文 斯高帕斯（Scopus） -
2001
Designing a modern memory hierarchy with hardware prefetching
Lin, W. F., Reinhardt, S. K. & Burger, D. B., 2001 11月, 於: IEEE Transactions on Computers. 50, 11, p. 1202-1218 17 p.研究成果: Article › 同行評審
32 引文 斯高帕斯（Scopus） -
Filtering superfluous prefetches using density vectors
Lin, W. F., Reinhardt, S. K., Burger, D. & Puzak, T. R., 2001, 於: Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. p. 124-132 9 p., 21.研究成果: Article › 同行評審
29 引文 斯高帕斯（Scopus） -
Reducing DRAM latencies with an integrated memory hierarchy design
Lin, W. F., Reinhardt, S. K. & Burger, D., 2001, p. 301-312. 12 p.研究成果: Paper › 同行評審
140 引文 斯高帕斯（Scopus）