In this paper, a 0.75-V CMOS logic operated in sub threshold region is proposed. Based on dynamic substrate bias, the supply voltage of the circuit is effectively reduced. Using UMC 0.5-μm CMOS technology, the logic circuits are verified by inverter function, NOR gate, exclusive OR gate, full adder, and ring oscillator. Including I/O pad capacitance, the results of the chip measurement show that the response time of this circuit is order of 100 μs under 0.75-V supply.
|出版狀態||Published - 2004 12月 1|
|事件||2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology - Tainan, Taiwan|
持續時間: 2004 12月 6 → 2004 12月 9
|Other||2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology|
|期間||04-12-06 → 04-12-09|
All Science Journal Classification (ASJC) codes