0.75-V subthreshold CMOS logic using dynamic substrate bias

Yu Cherng Hung, Bin Da Liu

研究成果: Paper

1 引文 斯高帕斯(Scopus)

摘要

In this paper, a 0.75-V CMOS logic operated in sub threshold region is proposed. Based on dynamic substrate bias, the supply voltage of the circuit is effectively reduced. Using UMC 0.5-μm CMOS technology, the logic circuits are verified by inverter function, NOR gate, exclusive OR gate, full adder, and ring oscillator. Including I/O pad capacitance, the results of the chip measurement show that the response time of this circuit is order of 100 μs under 0.75-V supply.

原文English
頁面345-348
頁數4
出版狀態Published - 2004 十二月 1
事件2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology - Tainan, Taiwan
持續時間: 2004 十二月 62004 十二月 9

Other

Other2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology
國家Taiwan
城市Tainan
期間04-12-0604-12-09

    指紋

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

引用此

Hung, Y. C., & Liu, B. D. (2004). 0.75-V subthreshold CMOS logic using dynamic substrate bias. 345-348. 論文發表於 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology, Tainan, Taiwan.