1-V bulk-driven CMOS analog programmable winner-takes-all circuit

Yu Cherng Hung, Bin Da Liu, Chung Yang Tsai

研究成果: Article同行評審

7 引文 斯高帕斯(Scopus)

摘要

In this paper, a 1-V bulk-driven analog winner-takes-all circuit with programmable k-winners capability is proposed. By presetting a set of binary bits, the desired k-winners-take-all or k-losers-take-all function is programmable. The proposed upward-and-downward searching greatly improves the response time. The chip has been fabricated with a 0.25-μm CMOS technology. Simulated results show that the response time of the winner-takes-all circuit is 50 μs under 5-mV identified resolution. The input range is approximately to be rail-to-rail.

原文English
頁(從 - 到)53-61
頁數9
期刊Analog Integrated Circuits and Signal Processing
49
發行號1
DOIs
出版狀態Published - 2006 十月

All Science Journal Classification (ASJC) codes

  • 訊號處理
  • 硬體和架構
  • 表面、塗料和薄膜

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