1-V CMOS similarity measurement chip for binary pattern identification

Yu Cherng Hung, Bin Da Liu

研究成果: Paper同行評審

1 引文 斯高帕斯(Scopus)

摘要

Design of a new low-voltage similarity measurement circuit is proposed in this paper. The similarity measurement between two binary patterns is represented by Hamming metric, that is, average absolute differential function. Using clock bootstrapped and level shift techniques, the supply voltage of the circuit is reduced to 1 V, which can efficiently operate within a battery supply. Some simple elements such as capacitor array, switch, and exclusive NOR gates are adopted to achieve Hamming metric function. An experimental chip is implemented by using a 0.25 μm CMOS technology. The simulation results show the circuit responds a 21-mV difference for each one-pixel difference between two binary patterns. The patterns have dimension 6×4 pixels.

原文English
頁面36-39
頁數4
出版狀態Published - 2005 十月 31
事件9th IEEE International Workshop on Cellular Neural Networks and their Applications, CNNA - Hsinchu, Taiwan
持續時間: 2005 五月 282005 五月 30

Other

Other9th IEEE International Workshop on Cellular Neural Networks and their Applications, CNNA
國家/地區Taiwan
城市Hsinchu
期間05-05-2805-05-30

All Science Journal Classification (ASJC) codes

  • 軟體

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