1-V rail-to-rail analog CMOS programmable winner-take-all chip with two-side searching capability for neurocomputing applications

Yu Cherng Hung, Chung Yang Tsai, Bin Da Liu

研究成果: Conference contribution

5 引文 斯高帕斯(Scopus)

摘要

A 1-V analog CMOS winner-take-all circuit with programmable k-winner-take-all and k-loser-take-all capabilities is proposed. The proposed up-and-down searching greatly improves the response time. By setting binary signals, the desired k-winner-take-all function or k-loser-take-all function is achieved, without modifying circuit structure. The circuit is verified by TSMC 0.25-μm CMOS technology. The results of post-layout simulation show that the response time of this circuit is 50 μs under 5-mV identified resolution. The dynamic range allows to be rail-to-rail input.

原文English
主出版物標題Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03
頁面337-340
頁數4
DOIs
出版狀態Published - 2003
事件2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03 - Nanjing, China
持續時間: 2003 十二月 142003 十二月 17

出版系列

名字Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03
1

Other

Other2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03
國家/地區China
城市Nanjing
期間03-12-1403-12-17

All Science Journal Classification (ASJC) codes

  • 訊號處理
  • 電腦網路與通信

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