10-bit 30-MS/s SAR ADC using a switchback switching method

Guan Ying Huang, Soon Jyh Chang, Chun Cheng Liu, Ying Zu Lin

研究成果: Article

63 引文 斯高帕斯(Scopus)

摘要

This brief presents a 10-bit 30-MS/s successive-approximation-register analog-to-digital converter (ADC) that uses a power efficient switchback switching method. With respect to the monotonic switching method, the input common-mode voltage variation reduces which improves the dynamic offset and the parasitic capacitance variation of the comparator. The proposed switchback switching method does not consume any power at the first digital-to-analog converter switching, which can reduce the power consumption and design effort of the reference buffer. The prototype was fabricated in a 90-nm 1P9M CMOS technology. At 1-V supply and 30 MS/s, the ADC achieves an sequenced neighbor double reservation of 56.89 dB and consumes 0.98 mW, resulting in a figure-of-merit (FOM) of 57 fJ/conversion-step. The ADC core occupies an active area of only 190×,525 μm2.

原文English
文章編號6172687
頁(從 - 到)584-588
頁數5
期刊IEEE Transactions on Very Large Scale Integration (VLSI) Systems
21
發行號3
DOIs
出版狀態Published - 2013 三月 11

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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