100-Channel wireless neural recording system with 54-Mb/s data link and 40%-efficiency power link

Kuang-Wei Cheng, Xiaodan Zou, Jia Hao Cheong, Rui Feng Xue, Zhiming Chen, Lei Yao, Hyouk Kyu Cha, San Jeow Cheng, Peng Li, Lei Liu, Luis Andia, Chee Keong Ho, Ming Yuan Cheng, Zhu Duan, Ramamoorthy Rajkumar, Yuanjin Zheng, Wang Ling Goh, Yongxin Guo, Gavin Dawe, Woo Tae ParkMinkyu Je

研究成果: Paper

17 引文 斯高帕斯(Scopus)

摘要

For real-time monitoring of brain activities, a highdata-rate, low-power, and highly mobile neural recording system is desirable. This paper presents a complete chipset for a 100-channel wireless neural recording system, which consists of 3 ICs - a neural interface (NI) IC and a wireless power RX and data TX IC for an implant unit (IU), and a wireless data RX IC for an external head unit (EHU). With a dual S/H NI architecture and a burst-mode (BM) wideband (WB) FSK TX, the IU achieves a 100-channel recording and wireless transmission at 54.24Mb/s while consuming only 6.6mW. Using power coupling with optimal resonant load transformation and high-efficiency rectifier and LDO circuits, the whole wireless power link achieves 40% efficiency over 1cm distance with 0.5cm tissue in between. The EHU needs to transmit the RF power lower than 30mW to operate the IU. The EHU is implemented using a crystal-less BM WB FSK RX consuming only 14.4mW at 27.12Mb/s.

原文English
頁面185-188
頁數4
DOIs
出版狀態Published - 2012 十二月 1
事件2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012 - Kobe, Japan
持續時間: 2012 十一月 122012 十一月 14

Other

Other2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012
國家Japan
城市Kobe
期間12-11-1212-11-14

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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    Cheng, K-W., Zou, X., Cheong, J. H., Xue, R. F., Chen, Z., Yao, L., Cha, H. K., Cheng, S. J., Li, P., Liu, L., Andia, L., Ho, C. K., Cheng, M. Y., Duan, Z., Rajkumar, R., Zheng, Y., Goh, W. L., Guo, Y., Dawe, G., ... Je, M. (2012). 100-Channel wireless neural recording system with 54-Mb/s data link and 40%-efficiency power link. 185-188. 論文發表於 2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012, Kobe, Japan. https://doi.org/10.1109/IPEC.2012.6522656