27.6 Background Capacitor-Current-Sensor Calibration of DC-DC Buck Converter with DVS for Accurately Accelerating Load-Transient Response

Tai Haur Kuo, Yi Wei Huang, Pai Yi Wang

研究成果: Conference contribution

1 引文 斯高帕斯(Scopus)

摘要

Switching buck converters with dynamic voltage scaling (DVS) for high-efficiency high-performance computing applications need to reduce the output-voltage undershoot/overshoot (V-{ {US}}/V-{ {OS}}) and settling time t-{ {S}} under a large and fast-changing load current (I-{ {load}}). A multiphase topology with a fast load-transient response meets these requirements. The load-transient response can be accurately accelerated to reduce V-{ {US}}/V-{ {OS}} and t-{ {S}} to near their ideal values by measuring the output-capacitor current I-{ {C} {o}} to control the inductor's energizing and de-energizing times, since I-{ {C} {o}} instantly reflects the load-current transients. An integrated capacitor-current sensor (CCS) [1] can be used to sense I-{ {C} {o}} by emulating the output-capacitor impedance Z-{ {C} {o}}: comprising capacitance C-{{O}}, the equivalent series resistance R-{ {E} {S} {R}}, and inductance L-{ {E} {S} {L}}. However, I-{ {C} {o}} will be inaccurately sensed if Z-{ {C} {o}} varies with different output voltages V-{{O}}, manufacturing variations, PCB parasitics, temperature, and aging. The state-of-the-art CCS calibration technique [1] for such Z-{ {C} {o}} variations is suitable for foreground operation and DVS with pre-characterized V-{{O}} levels, since calibration starts immediately after being enabled and runs continuously until it ends. The CCS in [1] is calibrated with a low-power cost-effective comparator and successive approximation logic, with an acceptable calibration time T-{{CAL}} for foreground operation. To broaden the range of applications, this work proposes an ADC-based CCS and a background CCS calibration (BCC) controller. The proposed CCS uses a flash ADC with a dynamic reference to shorten T-{ {C} {A} {L}}. The BCC controller automatically finds a quasi-steady state (OS), namely a short period of steady-state behavior when there is no load transient or DVS event, to trigger CCS calibration, and can interrupt CCS calibration when a load transient or a DVS event occurs. Since OSs generally exist, the BCC with a short T-{{CAL}} can increase the flexibility of scheduling both load transients and DVS events. Thus, it is suitable for DVS with numerous V-{{O}} levels that account for in situ parameter variations.

原文English
主出版物標題2019 IEEE International Solid-State Circuits Conference, ISSCC 2019
發行者Institute of Electrical and Electronics Engineers Inc.
頁面430-432
頁數3
ISBN(電子)9781538685310
DOIs
出版狀態Published - 2019 三月 6
事件2019 IEEE International Solid-State Circuits Conference, ISSCC 2019 - San Francisco, United States
持續時間: 2019 二月 172019 二月 21

出版系列

名字Digest of Technical Papers - IEEE International Solid-State Circuits Conference
2019-February
ISSN(列印)0193-6530

Conference

Conference2019 IEEE International Solid-State Circuits Conference, ISSCC 2019
國家United States
城市San Francisco
期間19-02-1719-02-21

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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