3D-IC interconnect test, diagnosis, and repair

Chun Chuan Chi, Cheng Wen Wu, Min Jer Wang, Hung Chih Lin

研究成果: Conference contribution

39 引文 斯高帕斯(Scopus)


Through-Silicon-Via (TSV)-based three-dimensional ICs (3D-ICs) have gained increasing attention due to their potential in reducing manufacturing costs and capability of integrating more functionality into a single chip. One of the most important factors that affect 3D-IC yield is the integrity of interconnects which connect different dies in a 3D-IC. This paper proposes a Design-for-Test (DIT) scheme that can 1) detect faulty interconnects in 3D-ICs, 2) pinpoint open defect locations to help yield learning, and 3) repair faulty interconnects caused by open defects to improve the 3D-IC yield. Experimental results show that the proposed scheme can achieve a diagnosis resolution of 84% for open defects. With the interconnect repair mechanism, the 3D-IC yield is improved by 10%. In addition, cost-benefit analysis reveals that the proposed technique can significantly increase the net profit, especially when the natural interconnect yield is low.

主出版物標題Proceedings - 2013 IEEE 31st VLSI Test Symposium, VTS 2013
出版狀態Published - 2013 8月 14
事件2013 IEEE 31st VLSI Test Symposium, VTS 2013 - Berkeley, CA, United States
持續時間: 2013 4月 292013 5月 1


名字Proceedings of the IEEE VLSI Test Symposium


Conference2013 IEEE 31st VLSI Test Symposium, VTS 2013
國家/地區United States
城市Berkeley, CA

All Science Journal Classification (ASJC) codes

  • 電腦科學應用
  • 電氣與電子工程


深入研究「3D-IC interconnect test, diagnosis, and repair」主題。共同形成了獨特的指紋。