TY - GEN
T1 - 3D-IC interconnect test, diagnosis, and repair
AU - Chi, Chun Chuan
AU - Wu, Cheng Wen
AU - Wang, Min Jer
AU - Lin, Hung Chih
PY - 2013/8/14
Y1 - 2013/8/14
N2 - Through-Silicon-Via (TSV)-based three-dimensional ICs (3D-ICs) have gained increasing attention due to their potential in reducing manufacturing costs and capability of integrating more functionality into a single chip. One of the most important factors that affect 3D-IC yield is the integrity of interconnects which connect different dies in a 3D-IC. This paper proposes a Design-for-Test (DIT) scheme that can 1) detect faulty interconnects in 3D-ICs, 2) pinpoint open defect locations to help yield learning, and 3) repair faulty interconnects caused by open defects to improve the 3D-IC yield. Experimental results show that the proposed scheme can achieve a diagnosis resolution of 84% for open defects. With the interconnect repair mechanism, the 3D-IC yield is improved by 10%. In addition, cost-benefit analysis reveals that the proposed technique can significantly increase the net profit, especially when the natural interconnect yield is low.
AB - Through-Silicon-Via (TSV)-based three-dimensional ICs (3D-ICs) have gained increasing attention due to their potential in reducing manufacturing costs and capability of integrating more functionality into a single chip. One of the most important factors that affect 3D-IC yield is the integrity of interconnects which connect different dies in a 3D-IC. This paper proposes a Design-for-Test (DIT) scheme that can 1) detect faulty interconnects in 3D-ICs, 2) pinpoint open defect locations to help yield learning, and 3) repair faulty interconnects caused by open defects to improve the 3D-IC yield. Experimental results show that the proposed scheme can achieve a diagnosis resolution of 84% for open defects. With the interconnect repair mechanism, the 3D-IC yield is improved by 10%. In addition, cost-benefit analysis reveals that the proposed technique can significantly increase the net profit, especially when the natural interconnect yield is low.
UR - http://www.scopus.com/inward/record.url?scp=84881290625&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84881290625&partnerID=8YFLogxK
U2 - 10.1109/VTS.2013.6548905
DO - 10.1109/VTS.2013.6548905
M3 - Conference contribution
AN - SCOPUS:84881290625
SN - 9781467355438
T3 - Proceedings of the IEEE VLSI Test Symposium
BT - Proceedings - 2013 IEEE 31st VLSI Test Symposium, VTS 2013
T2 - 2013 IEEE 31st VLSI Test Symposium, VTS 2013
Y2 - 29 April 2013 through 1 May 2013
ER -