3D-IC test architecture for TSVs with different impact ranges of crosstalk faults

Wen Hsuan Hsu, Michael A. Kochte, Kuen Jong Lee

研究成果: Conference contribution

2 引文 (Scopus)

摘要

Through Silicon Vias (TSV) play an important role in 3D chip integration. Its features include: providing vertical interconnection, decreasing the area of routing, and increasing the bandwidth. Effective and efficient testing for correct operation of TSVs is an essential issue for 3D ICs. This work focuses on crosstalk faults with different impact ranges and proposes a TSV grouping method to test as many TSVs simultaneously as possible. Based on the results of the TSV grouping, we also implement a high-efficiency, low-area-overhead TSV test architecture.

原文English
主出版物標題2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781467394987
DOIs
出版狀態Published - 2016 五月 31
事件2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016 - Hsinchu, Taiwan
持續時間: 2016 四月 252016 四月 27

出版系列

名字2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016

Other

Other2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016
國家Taiwan
城市Hsinchu
期間16-04-2516-04-27

指紋

Crosstalk
crosstalk
Silicon
silicon
chips
bandwidth
Bandwidth
Testing

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality
  • Instrumentation

引用此文

Hsu, W. H., Kochte, M. A., & Lee, K. J. (2016). 3D-IC test architecture for TSVs with different impact ranges of crosstalk faults. 於 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016 [7482554] (2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-DAT.2016.7482554
Hsu, Wen Hsuan ; Kochte, Michael A. ; Lee, Kuen Jong. / 3D-IC test architecture for TSVs with different impact ranges of crosstalk faults. 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016. Institute of Electrical and Electronics Engineers Inc., 2016. (2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016).
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title = "3D-IC test architecture for TSVs with different impact ranges of crosstalk faults",
abstract = "Through Silicon Vias (TSV) play an important role in 3D chip integration. Its features include: providing vertical interconnection, decreasing the area of routing, and increasing the bandwidth. Effective and efficient testing for correct operation of TSVs is an essential issue for 3D ICs. This work focuses on crosstalk faults with different impact ranges and proposes a TSV grouping method to test as many TSVs simultaneously as possible. Based on the results of the TSV grouping, we also implement a high-efficiency, low-area-overhead TSV test architecture.",
author = "Hsu, {Wen Hsuan} and Kochte, {Michael A.} and Lee, {Kuen Jong}",
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Hsu, WH, Kochte, MA & Lee, KJ 2016, 3D-IC test architecture for TSVs with different impact ranges of crosstalk faults. 於 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016., 7482554, 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016, Institute of Electrical and Electronics Engineers Inc., 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016, Hsinchu, Taiwan, 16-04-25. https://doi.org/10.1109/VLSI-DAT.2016.7482554

3D-IC test architecture for TSVs with different impact ranges of crosstalk faults. / Hsu, Wen Hsuan; Kochte, Michael A.; Lee, Kuen Jong.

2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016. Institute of Electrical and Electronics Engineers Inc., 2016. 7482554 (2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016).

研究成果: Conference contribution

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AU - Kochte, Michael A.

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PY - 2016/5/31

Y1 - 2016/5/31

N2 - Through Silicon Vias (TSV) play an important role in 3D chip integration. Its features include: providing vertical interconnection, decreasing the area of routing, and increasing the bandwidth. Effective and efficient testing for correct operation of TSVs is an essential issue for 3D ICs. This work focuses on crosstalk faults with different impact ranges and proposes a TSV grouping method to test as many TSVs simultaneously as possible. Based on the results of the TSV grouping, we also implement a high-efficiency, low-area-overhead TSV test architecture.

AB - Through Silicon Vias (TSV) play an important role in 3D chip integration. Its features include: providing vertical interconnection, decreasing the area of routing, and increasing the bandwidth. Effective and efficient testing for correct operation of TSVs is an essential issue for 3D ICs. This work focuses on crosstalk faults with different impact ranges and proposes a TSV grouping method to test as many TSVs simultaneously as possible. Based on the results of the TSV grouping, we also implement a high-efficiency, low-area-overhead TSV test architecture.

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M3 - Conference contribution

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BT - 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016

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Hsu WH, Kochte MA, Lee KJ. 3D-IC test architecture for TSVs with different impact ranges of crosstalk faults. 於 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016. Institute of Electrical and Electronics Engineers Inc. 2016. 7482554. (2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016). https://doi.org/10.1109/VLSI-DAT.2016.7482554