3D integration of vertical-stacking of MoS2and Si CMOS featuring embedded 2T1R configuration demonstrated on full wafers

C. J. Su, M. K. Huang, K. S. Lee, V. P.H. Hu, Y. F. Huang, B. C. Zheng, C. H. Yao, N. C. Lin, K. H. Kao, T. C. Hong, P. J. Sung, C. T. Wu, T. Y. Yu, K. L. Lin, Y. C. Tseng, C. L. Lin, Y. J. Lee, T. S. Chao, J. Y. Li, W. F. WuJ. M. Shieh, Y. H. Wang, W. K. Yeh

研究成果: Conference contribution

摘要

For the first time, a 3D stacking of MoS2 and Si CMOS integrated with embedded RRAM is proposed and fabricated, and CMOS inverter comprised of MoS2 nFET and Si pFET is demonstrated. Vertically stacked multiple MoS2 channels are required for the performance matching. Resistive switching (RS) of a Ti/MoS2 /p+-Si structure showing high ON/OFF ratio of 106 is demonstrated firstly by highly Si-compatible process. Surface modification is the key to formation of uniform and smooth stacked MoS2 multiple channels and to enhanced resistive switching endurance. This scheme can be applied to CMOS-based bipolar RRAM 1T1R or 2T1R without increasing the cell size. Our work offers a new pathway with high feasibility of integrated 2D materials and Si FETs into CMOS to enabling 3D embedded logics and memories for future computing systems.

原文English
主出版物標題2020 IEEE International Electron Devices Meeting, IEDM 2020
發行者Institute of Electrical and Electronics Engineers Inc.
頁面12.2.1-12.2.4
ISBN(電子)9781728188881
DOIs
出版狀態Published - 2020 十二月 12
事件66th Annual IEEE International Electron Devices Meeting, IEDM 2020 - Virtual, San Francisco, United States
持續時間: 2020 十二月 122020 十二月 18

出版系列

名字Technical Digest - International Electron Devices Meeting, IEDM
2020-December
ISSN(列印)0163-1918

Conference

Conference66th Annual IEEE International Electron Devices Meeting, IEDM 2020
國家United States
城市Virtual, San Francisco
期間20-12-1220-12-18

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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