TY - GEN
T1 - 3D integration opportunities, issues, and solutions
T2 - 2009 Lithography Asia Conference
AU - Kwai, Ding Ming
AU - Wu, Cheng Wen
PY - 2009/12/1
Y1 - 2009/12/1
N2 - As the development cost of a typical system-on-chip (SOC) using state-of-the-art technology soars, more and more people turn to three-dimensional (3D) integration for possible alternatives that provide better or equal performance with lower cost. Stacking dies using the through-silicon-via (TSV) technology has been considered one of the most promising solutions to extending the life of Moore's law in semiconductor industry, but of course there are problems to be solved before the infrastructure can be set up to support the industry for manufacturing TSV-based 3D integrated devices. In this paper we will discuss the opportunities, design and manufacturing issues, and possible solutions for 3D integrated devices, from a designer's perspective.
AB - As the development cost of a typical system-on-chip (SOC) using state-of-the-art technology soars, more and more people turn to three-dimensional (3D) integration for possible alternatives that provide better or equal performance with lower cost. Stacking dies using the through-silicon-via (TSV) technology has been considered one of the most promising solutions to extending the life of Moore's law in semiconductor industry, but of course there are problems to be solved before the infrastructure can be set up to support the industry for manufacturing TSV-based 3D integrated devices. In this paper we will discuss the opportunities, design and manufacturing issues, and possible solutions for 3D integrated devices, from a designer's perspective.
UR - http://www.scopus.com/inward/record.url?scp=77952079733&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=77952079733&partnerID=8YFLogxK
U2 - 10.1117/12.845747
DO - 10.1117/12.845747
M3 - Conference contribution
AN - SCOPUS:77952079733
SN - 9780819479099
T3 - Proceedings of SPIE - The International Society for Optical Engineering
BT - Lithography Asia 2009
Y2 - 18 November 2009 through 19 November 2009
ER -