50 nm vertical surround gate MOSFET with S-factor of 75mV/dec

R. Li, Y. Zhang, Y. Lu, Sung Choi Daniel Sung Choi, M. Luo, K. L. Wang

研究成果: Paper同行評審

4 引文 斯高帕斯(Scopus)

摘要

Fully depleted vertical metal oxide semiconductor field effect transistors (MOSFET) were fabricated, characterized. A self-aligned process was used to fabricate the structure on silicon walls. The vertical MOSFET exposed by focus ion microbeam milling was analyzed by scanning electron microscopy.

原文English
頁面63-64
頁數2
出版狀態Published - 2001
事件Device Research Conference (DRC) - Notre Dame, IN, United States
持續時間: 2001 六月 252001 六月 27

Conference

ConferenceDevice Research Conference (DRC)
國家/地區United States
城市Notre Dame, IN
期間01-06-2501-06-27

All Science Journal Classification (ASJC) codes

  • 工程 (全部)

指紋

深入研究「50 nm vertical surround gate MOSFET with S-factor of 75mV/dec」主題。共同形成了獨特的指紋。

引用此