6-T SRAM cell design with gate-all-around silicon nanowire MOSFETs

Yi Bo Liao, Meng Hsueh Chiang, Nattapol Damrongplasit, Tsu Jae King Liu, Wei Chou Hsu

研究成果: Conference contribution

8 引文 斯高帕斯(Scopus)

摘要

6T-SRAM cell design with gate-all-around (GAA) silicon nanowire (NW) MOSFETs is investigated via three-dimensional TCAD simulations and compact analytical modeling. A rectangular NW channel design allows the transistor width to be adjusted with reduced impact on short-channel effects. This in turn provides a means for tuning the cell ratios to optimize the tradeoff between static noise margin and writeability with optimal cell layout area efficiency.

原文English
主出版物標題2013 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2013
DOIs
出版狀態Published - 2013 八月 12
事件2013 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2013 - Hsinchu, Taiwan
持續時間: 2013 四月 222013 四月 24

出版系列

名字2013 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2013

Other

Other2013 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2013
國家Taiwan
城市Hsinchu
期間13-04-2213-04-24

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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    Liao, Y. B., Chiang, M. H., Damrongplasit, N., Liu, T. J. K., & Hsu, W. C. (2013). 6-T SRAM cell design with gate-all-around silicon nanowire MOSFETs. 於 2013 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2013 [6545631] (2013 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2013). https://doi.org/10.1109/VLSI-TSA.2013.6545631