6-T SRAM performance assessment with stacked silicon nanowire MOSFETs

Ya Chi Huang, Meng-Hsueh Chiang, Wei-Chou Hsu, Shiou Ying Cheng

研究成果: Conference contribution

2 引文 (Scopus)

摘要

This paper assesses the 6-T SRAM performance and provides the design methodology with stacked gate-all-around silicon nanowire (NW) MOSFETs. To achieve high density design while preserving performance, different numbers of stacked NW MOSFETs are investigated via three-dimensional TCAD simulation. Due to tradeoff between read stability and writeability margins, adjusting the relative strengths of the transistors is needed but it can not be done straightforwardly as the widths of transistors are now quantized. Furthermore, when 3D stacking nanowires technique is used, another design issue with various stacked transistors has to be taken into account. This work simulates butterfly curves and N-curves to assess the device performance and provides an optimal design methodology for feasible manufacturability and good performance while using high density stacking technique. It is suggested that for the same stacked layers, though high stacking number favors writeability, it is limited to three layers due to source/drain series resistances. The double stacking is feasible for balanced read and write performances.

原文English
主出版物標題Proceedings of the 16th International Symposium on Quality Electronic Design, ISQED 2015
發行者IEEE Computer Society
頁面610-614
頁數5
ISBN(電子)9781479975815
DOIs
出版狀態Published - 2015 四月 13
事件16th International Symposium on Quality Electronic Design, ISQED 2015 - Santa Clara, United States
持續時間: 2015 三月 22015 三月 4

出版系列

名字Proceedings - International Symposium on Quality Electronic Design, ISQED
2015-April
ISSN(列印)1948-3287
ISSN(電子)1948-3295

Other

Other16th International Symposium on Quality Electronic Design, ISQED 2015
國家United States
城市Santa Clara
期間15-03-0215-03-04

指紋

Static random access storage
Nanowires
Transistors
Silicon

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

引用此文

Huang, Y. C., Chiang, M-H., Hsu, W-C., & Cheng, S. Y. (2015). 6-T SRAM performance assessment with stacked silicon nanowire MOSFETs. 於 Proceedings of the 16th International Symposium on Quality Electronic Design, ISQED 2015 (頁 610-614). [7085497] (Proceedings - International Symposium on Quality Electronic Design, ISQED; 卷 2015-April). IEEE Computer Society. https://doi.org/10.1109/ISQED.2015.7085497
Huang, Ya Chi ; Chiang, Meng-Hsueh ; Hsu, Wei-Chou ; Cheng, Shiou Ying. / 6-T SRAM performance assessment with stacked silicon nanowire MOSFETs. Proceedings of the 16th International Symposium on Quality Electronic Design, ISQED 2015. IEEE Computer Society, 2015. 頁 610-614 (Proceedings - International Symposium on Quality Electronic Design, ISQED).
@inproceedings{bff92962f38e4af589e694366ae6dd83,
title = "6-T SRAM performance assessment with stacked silicon nanowire MOSFETs",
abstract = "This paper assesses the 6-T SRAM performance and provides the design methodology with stacked gate-all-around silicon nanowire (NW) MOSFETs. To achieve high density design while preserving performance, different numbers of stacked NW MOSFETs are investigated via three-dimensional TCAD simulation. Due to tradeoff between read stability and writeability margins, adjusting the relative strengths of the transistors is needed but it can not be done straightforwardly as the widths of transistors are now quantized. Furthermore, when 3D stacking nanowires technique is used, another design issue with various stacked transistors has to be taken into account. This work simulates butterfly curves and N-curves to assess the device performance and provides an optimal design methodology for feasible manufacturability and good performance while using high density stacking technique. It is suggested that for the same stacked layers, though high stacking number favors writeability, it is limited to three layers due to source/drain series resistances. The double stacking is feasible for balanced read and write performances.",
author = "Huang, {Ya Chi} and Meng-Hsueh Chiang and Wei-Chou Hsu and Cheng, {Shiou Ying}",
year = "2015",
month = "4",
day = "13",
doi = "10.1109/ISQED.2015.7085497",
language = "English",
series = "Proceedings - International Symposium on Quality Electronic Design, ISQED",
publisher = "IEEE Computer Society",
pages = "610--614",
booktitle = "Proceedings of the 16th International Symposium on Quality Electronic Design, ISQED 2015",
address = "United States",

}

Huang, YC, Chiang, M-H, Hsu, W-C & Cheng, SY 2015, 6-T SRAM performance assessment with stacked silicon nanowire MOSFETs. 於 Proceedings of the 16th International Symposium on Quality Electronic Design, ISQED 2015., 7085497, Proceedings - International Symposium on Quality Electronic Design, ISQED, 卷 2015-April, IEEE Computer Society, 頁 610-614, 16th International Symposium on Quality Electronic Design, ISQED 2015, Santa Clara, United States, 15-03-02. https://doi.org/10.1109/ISQED.2015.7085497

6-T SRAM performance assessment with stacked silicon nanowire MOSFETs. / Huang, Ya Chi; Chiang, Meng-Hsueh; Hsu, Wei-Chou; Cheng, Shiou Ying.

Proceedings of the 16th International Symposium on Quality Electronic Design, ISQED 2015. IEEE Computer Society, 2015. p. 610-614 7085497 (Proceedings - International Symposium on Quality Electronic Design, ISQED; 卷 2015-April).

研究成果: Conference contribution

TY - GEN

T1 - 6-T SRAM performance assessment with stacked silicon nanowire MOSFETs

AU - Huang, Ya Chi

AU - Chiang, Meng-Hsueh

AU - Hsu, Wei-Chou

AU - Cheng, Shiou Ying

PY - 2015/4/13

Y1 - 2015/4/13

N2 - This paper assesses the 6-T SRAM performance and provides the design methodology with stacked gate-all-around silicon nanowire (NW) MOSFETs. To achieve high density design while preserving performance, different numbers of stacked NW MOSFETs are investigated via three-dimensional TCAD simulation. Due to tradeoff between read stability and writeability margins, adjusting the relative strengths of the transistors is needed but it can not be done straightforwardly as the widths of transistors are now quantized. Furthermore, when 3D stacking nanowires technique is used, another design issue with various stacked transistors has to be taken into account. This work simulates butterfly curves and N-curves to assess the device performance and provides an optimal design methodology for feasible manufacturability and good performance while using high density stacking technique. It is suggested that for the same stacked layers, though high stacking number favors writeability, it is limited to three layers due to source/drain series resistances. The double stacking is feasible for balanced read and write performances.

AB - This paper assesses the 6-T SRAM performance and provides the design methodology with stacked gate-all-around silicon nanowire (NW) MOSFETs. To achieve high density design while preserving performance, different numbers of stacked NW MOSFETs are investigated via three-dimensional TCAD simulation. Due to tradeoff between read stability and writeability margins, adjusting the relative strengths of the transistors is needed but it can not be done straightforwardly as the widths of transistors are now quantized. Furthermore, when 3D stacking nanowires technique is used, another design issue with various stacked transistors has to be taken into account. This work simulates butterfly curves and N-curves to assess the device performance and provides an optimal design methodology for feasible manufacturability and good performance while using high density stacking technique. It is suggested that for the same stacked layers, though high stacking number favors writeability, it is limited to three layers due to source/drain series resistances. The double stacking is feasible for balanced read and write performances.

UR - http://www.scopus.com/inward/record.url?scp=84944327782&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84944327782&partnerID=8YFLogxK

U2 - 10.1109/ISQED.2015.7085497

DO - 10.1109/ISQED.2015.7085497

M3 - Conference contribution

AN - SCOPUS:84944327782

T3 - Proceedings - International Symposium on Quality Electronic Design, ISQED

SP - 610

EP - 614

BT - Proceedings of the 16th International Symposium on Quality Electronic Design, ISQED 2015

PB - IEEE Computer Society

ER -

Huang YC, Chiang M-H, Hsu W-C, Cheng SY. 6-T SRAM performance assessment with stacked silicon nanowire MOSFETs. 於 Proceedings of the 16th International Symposium on Quality Electronic Design, ISQED 2015. IEEE Computer Society. 2015. p. 610-614. 7085497. (Proceedings - International Symposium on Quality Electronic Design, ISQED). https://doi.org/10.1109/ISQED.2015.7085497