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出版年份

  • 2020
  • 2019
  • 2018
  • 2017
  • 2016
  • 2015
  • 2014
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作者

  • Cheng-Wen Wu

3D-IC BISR for stacked memories using cross-die spares

Chi, C. C., Chou, Y. F., Kwai, D. M., Hsiao, Y. Y., Wu, C. W., Hsing, Y. T., Denq, L. M. & Lin, T. H., 2012 七月 25, 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers. 6212621. (2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers).

研究成果: Conference contribution

9 引文 斯高帕斯(Scopus)

3D-IC interconnect test, diagnosis, and repair

Chi, C. C., Wu, C. W., Wang, M. J. & Lin, H. C., 2013 八月 14, Proceedings - 2013 IEEE 31st VLSI Test Symposium, VTS 2013. 6548905. (Proceedings of the IEEE VLSI Test Symposium).

研究成果: Conference contribution

34 引文 斯高帕斯(Scopus)

A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS

Lin, T. J., Chien, C. A., Chang, P. Y., Chen, C. W., Wang, P. H., Shyu, T. Y., Chou, C. Y., Luo, S. C., Guo, J. I., Chen, T. F., Chuang, G. C. H., Chu, Y. H., Cheng, L. C., Su, H. M., Jou, C., Ieong, M., Wu, C. W. & Wang, J. S., 2013 四月 29, 2013 IEEE International Solid-State Circuits Conference, ISSCC 2013 - Digest of Technical Papers. p. 158-159 2 p. 6487680. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; 卷 56).

研究成果: Conference contribution

19 引文 斯高帕斯(Scopus)

A built-in self-diagnosis and repair design with fail pattern identification for memories

Su, C. L., Huang, R. F., Wu, C. W., Luo, K. L. & Wu, W. C., 2011 十二月 1, 於 : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 19, 12, p. 2184-2194 11 p., 5593911.

研究成果: Article

8 引文 斯高帕斯(Scopus)

A built-in self-test scheme for 3D RAMs

Yu, Y. C., Chou, C. W., Li, J. F., Lo, C. Y., Kwai, D. M., Chou, Y. F. & Wu, C. W., 2012 十二月 1, ITC 2012 - International Test Conference 2012, Proceedings. 6401579. (Proceedings - International Test Conference).

研究成果: Conference contribution

4 引文 斯高帕斯(Scopus)

A Built-in Self-Test Scheme for Detecting Defects in FinFET-Based SRAM Circuit

Chen, M. C., Wu, T. H. & Wu, C. W., 2018 十二月 6, Proceedings - 2018 IEEE 27th Asian Test Symposium, ATS 2018. IEEE Computer Society, p. 19-24 6 p. 8567404. (Proceedings of the Asian Test Symposium; 卷 2018-October).

研究成果: Conference contribution

1 引文 斯高帕斯(Scopus)

A built-in self-test scheme for the post-bond test of TSVs in 3D ICs

Huang, Y. J., Li, J. F., Chen, J. J., Kwai, D. M., Chou, Y. F. & Wu, C. W., 2011 七月 1, Proceedings - 2011 29th IEEE VLSI Test Symposium, VTS 2011. p. 20-25 6 p. 5783749. (Proceedings of the IEEE VLSI Test Symposium).

研究成果: Conference contribution

66 引文 斯高帕斯(Scopus)

A Built-Off Self-Repair Scheme for Channel-Based 3D Memories

Liu, H. H., Lin, B. Y., Wu, C. W., Chiang, W. T., Mincent, L., Lin, H. C., Peng, C. N. & Wang, M. J., 2017 八月 1, 於 : IEEE Transactions on Computers. 66, 8, p. 1293-1301 9 p., 7850958.

研究成果: Article

2 引文 斯高帕斯(Scopus)

A Computer Designed Half Gb 16-Channel 819Gb/s High-Bandwidth and 10ns Low-Latency DRAM for 3D Stacked Memory Devices Using TSVs

Wu, C-W., Luo, P-W., Chen, C-K., Sung, Y-H., Wu, W., Shih, H-C., Lee, C-H., Lee, K-H., Li, M-W., Lung, M-C., Lu, C-N., Chou, Y-F., Shih, P-L., Ke, C-H., Shiah, C., Stolt, P., Tomishima, S., Kwai, D-M., Rong, B-D., Lu, N. 及其他1, Lu, S-L., 2015 六月, IEEE Symp. VLSI Circuits (VLSI).

研究成果: Conference contribution

2 引文 斯高帕斯(Scopus)

AC-plus scan methodology for small delay testing and characterization

Li, T. Y., Huang, S. Y., Hsu, H. J., Tzeng, C. W., Huang, C. T., Liou, J. J., Ma, H. P., Huang, P. C., Bor, J. C., Tien, C. C., Wang, C. H. & Wu, C. W., 2013 一月 1, 於 : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 21, 2, p. 329-341 13 p., 6166352.

研究成果: Article

2 引文 斯高帕斯(Scopus)

A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive Devices

Pan, Y-C., Jian, Y-R., Liu, H-H. & Wu, C-W., 2018 七月, VLSI Test Technology Workshop (VTTW). Nantou

研究成果: Conference contribution

A fast sweep-line-based failure pattern extractor for memory diagnosis

Wei, S. Y., Lin, B. Y. & Wu, C. W., 2016 七月 22, Proceedings - 2016 21st IEEE European Test Symposium, ETS 2016. Institute of Electrical and Electronics Engineers Inc., 7519314. (Proceedings of the European Test Workshop; 卷 2016-July).

研究成果: Conference contribution

2 引文 斯高帕斯(Scopus)

A hybrid ECC and redundancy technique for reducing refresh power of DRAMs

Yu, Y. C., Hou, C. S., Chang, L. J., Li, J. F., Lo, C. Y., Kwai, D. M., Chou, Y. F. & Wu, C. W., 2013 八月 14, Proceedings - 2013 IEEE 31st VLSI Test Symposium, VTS 2013. 6548927. (Proceedings of the IEEE VLSI Test Symposium).

研究成果: Conference contribution

5 引文 斯高帕斯(Scopus)

A local parallel search approach for memory failure pattern identification

Lin, B. Y., Wu, C. W., Lee, M., Lin, H. C., Peng, C. N. & Wang, M. J., 2016 三月 1, 於 : IEEE Transactions on Computers. 65, 3, p. 770-780 11 p., 7173026.

研究成果: Article

3 引文 斯高帕斯(Scopus)

A low-cost wireless interface with no external antenna and crystal oscillator for Cm-range contactless testing

Li, C. F., Lee, C. Y., Wang, C. H., Chang, S. L., Denq, L. M., Chi, C. C., Hsu, H. J., Chu, M. Y., Liou, J. J., Huang, S. Y., Huang, P. C., Ma, H. P., Bor, J. C., Wu, C. W., Tien, C. C., Wang, C. H., Kuo, Y. S., Huang, C. T. & Chang, T. Y., 2011 九月 16, 2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011. p. 771-776 6 p. 5981870. (Proceedings - Design Automation Conference).

研究成果: Conference contribution

2 引文 斯高帕斯(Scopus)
26 引文 斯高帕斯(Scopus)

A memory failure pattern analyzer for memory diagnosis and repair

Lin, B. Y., Lee, M. & Wu, C. W., 2012 八月 20, Proceedings - 2012 30th IEEE VLSI Test Symposium, VTS 2012. p. 234-239 6 p. 6231059. (Proceedings of the IEEE VLSI Test Symposium).

研究成果: Conference contribution

9 引文 斯高帕斯(Scopus)

A memory yield improvement scheme combining built-in self-repair and error correction codes

Wu, T. H., Chen, P. Y., Lee, M., Lin, B. Y., Wu, C. W., Tien, C. H., Lin, H. C., Chen, H., Peng, C. N. & Wang, M. J., 2012 十二月 1, ITC 2012 - International Test Conference 2012, Proceedings. 6401576. (Proceedings - International Test Conference).

研究成果: Conference contribution

16 引文 斯高帕斯(Scopus)

Analytical modeling and numerical simulations of temperature field in TSV-based 3D ICs

Shiyanovskii, Y., Papachristou, C. & Wu, C. W., 2013 七月 5, Proceedings of the 14th International Symposium on Quality Electronic Design, ISQED 2013. p. 24-29 6 p. 6523585. (Proceedings - International Symposium on Quality Electronic Design, ISQED).

研究成果: Conference contribution

1 引文 斯高帕斯(Scopus)

An enhanced boundary scan architecture for inter-die interconnect leakage measurement in 2.5D and 3D packages

Law, P. M. P., Wu, C. W., Lin, L. Y. & Hong, H. C., 2018 一月 24, Proceedings - 2017 IEEE 26th Asian Test Symposium, ATS 2017. Taipei: IEEE Computer Society, p. 1-6 6 p. (Proceedings of the Asian Test Symposium).

研究成果: Conference contribution

An enhanced double-TSV Scheme for defect tolerance in 3D-IC

Shih, H. C. & Wu, C. W., 2013 十月 21, Proceedings - Design, Automation and Test in Europe, DATE 2013. p. 1486-1489 4 p. 6513748. (Proceedings -Design, Automation and Test in Europe, DATE).

研究成果: Conference contribution

2 引文 斯高帕斯(Scopus)

An FPGA-based test platform for analyzing data retention time distribution of DRAMs

Hou, C. S., Li, J. F., Lo, C. Y., Kwai, D. M., Chou, Y. F. & Wu, C. W., 2013 八月 15, 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013. 6533853. (2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013).

研究成果: Conference contribution

11 引文 斯高帕斯(Scopus)

Application-independent testing of 3-D field programmable gate array interconnect faults

Peng, Y. L., Kwai, D. M., Chou, Y. F. & Wu, C. W., 2014 二月 1, 於 : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 22, 2, p. 207-219 13 p., 6459051.

研究成果: Article

5 引文 斯高帕斯(Scopus)

A Self-Organizing Map-Based Adaptive Traffic Light Control System with Reinforcement Learning

Kao, Y. C. & Wu, C. W., 2019 二月 19, Conference Record of the 52nd Asilomar Conference on Signals, Systems and Computers, ACSSC 2018. Matthews, M. B. (編輯). IEEE Computer Society, p. 2060-2064 5 p. 8645125. (Conference Record - Asilomar Conference on Signals, Systems and Computers; 卷 2018-October).

研究成果: Conference contribution

A self-testing and calibration method for embedded successive approximation register ADC

Huang, X. L., Kang, P. Y., Chang, H. M., Huang, J. L., Chou, Y. F., Lee, Y. P., Kwai, D. M. & Wu, C. W., 2011 三月 28, 2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011. p. 713-718 6 p. 5722279. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

研究成果: Conference contribution

11 引文 斯高帕斯(Scopus)

A study on electric properties for pulse laser annealing of ITO film after wet etching

Lee, C. J., Lin, H. K., Li, C. H., Chen, L. X., Lee, C. C., Wu, C. W. & Huang, J. C., 2012 十一月 1, 於 : Thin Solid Films. 522, p. 330-335 6 p.

研究成果: Article

24 引文 斯高帕斯(Scopus)

Automated Probe-Mark Analysis

Wu, C-W., Jian, Y-R., Fodor, F. & Marinissen, E. J., 2018 六月, Semiconductor Wafer Test Workshop (SWTW).

研究成果: Conference contribution

BIST-assisted tuning scheme for minimizing io-channel power of TSV-based 3D DRAMs

Yu, Y. C., Yang, C. C., Li, J. F., Lo, C. Y., Chen, C. H., Lai, J. S., Kwai, D. M., Chou, Y. F. & Wu, C. W., 2014 十二月 7, Proceedings - 23rd Asian Test Symposium, ATS 2014. Hsinchu: IEEE Computer Society, p. 1-6 6 p. 06979068. (Proceedings of the Asian Test Symposium).

研究成果: Conference contribution

1 引文 斯高帕斯(Scopus)

Building a fault tolerant framework with deadline guarantee in big data stream computing environments

Sun, D., Zhang, G., Wu, C., Li, K. & Zheng, W., 2017 十一月, 於 : Journal of Computer and System Sciences. 89, p. 4-23 20 p.

研究成果: Article

11 引文 斯高帕斯(Scopus)

Built-in self-forming, built-in self-test, and built-in self-repair for RRAM yield improvement

Wu, C-W., Chen, C-Y., Shih, H-C., Lee, M., Lin, C-H. & Sheu, S-S., 2011 七月, VLSI Test Tech. Workshop (VTTW). Nantou

研究成果: Conference contribution

Cell-Aware Test Generation Time Reduction by Using Switch-Level ATPG

Wu, C-W., Chuang, P-Y. & Chen, H. H., 2017 九月, IEEE Int. Test Conf. in Asia (ITC-A). Taipei

研究成果: Conference contribution

Configurable Cubical Redundancy Schemes for Channel-Based 3-D DRAM Yield Improvement

Lin, B. Y., Chiang, W. T., Wu, C. W., Lee, M., Lin, H. C., Peng, C. N. & Wang, M. J., 2016 四月 1, 於 : IEEE Design and Test. 33, 2, p. 30-39 10 p., 7154435.

研究成果: Article

1 引文 斯高帕斯(Scopus)

Controller architecture for low-power, low-latency DRAM with built-in cache

Liu, Z. Y., Shih, H. C., Lin, B. Y. & Wu, C. W., 2017 四月 1, 於 : IEEE Design and Test. 34, 2, p. 69-78 10 p., 7397924.

研究成果: Article

1 引文 斯高帕斯(Scopus)

Cost modeling and analysis for interposer-based three-dimensional IC

Chou, Y. W., Chen, P. Y., Lee, M. & Wu, C. W., 2012 八月 20, Proceedings - 2012 30th IEEE VLSI Test Symposium, VTS 2012. p. 108-113 6 p. 6231088. (Proceedings of the IEEE VLSI Test Symposium).

研究成果: Conference contribution

9 引文 斯高帕斯(Scopus)

Covering hard-To-detect defects by thermal quorum sensing

Chuang, P. Y., Wu, C. W. & Chen, H. H., 2018 六月 29, Proceedings - 2018 23rd IEEE European Test Symposium, ETS 2018. Bremen: Institute of Electrical and Electronics Engineers Inc., p. 1-2 2 p. (Proceedings of the European Test Workshop; 卷 2018-May).

研究成果: Conference contribution

DArT: A component-based DRAM area, power, and timing modeling tool

Shih, H. C., Luo, P. W., Yeh, J. C., Lin, S. Y., Kwai, D. M., Lu, S. L., Schaefer, A. & Wu, C. W., 2014 一月 1, 於 : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 33, 9, p. 1356-1369 14 p., 6879579.

研究成果: Article

11 引文 斯高帕斯(Scopus)

DfT architecture for 3D-SICs with multiple towers

Chi, C. C., Marinissen, E. J., Goel, S. K. & Wu, C. W., 2011 八月 29, Proceedings - 16th IEEE European Test Symposium, ETS 2011. p. 51-56 6 p. 5957922. (Proceedings - 16th IEEE European Test Symposium, ETS 2011).

研究成果: Conference contribution

29 引文 斯高帕斯(Scopus)

DRAM system simulation speed-Up by effective-cycle selection

Chiang, H. C., Wang, M. Y. & Wu, C. W., 2014 一月 1, Proceedings - 2014 International Symposium on Computer, Consumer and Control, IS3C 2014. IEEE Computer Society, p. 1053-1056 4 p. 6846067. (Proceedings - 2014 International Symposium on Computer, Consumer and Control, IS3C 2014).

研究成果: Conference contribution

Efficient Cell-Aware Fault Modeling by Switch-Level Test Generation

Chen, H. H., Chen, S. Y. H., Chuang, P. Y. & Wu, C. W., 2016 十二月 22, Proceedings - 2016 IEEE 25th Asian Test Symposium, ATS 2016. IEEE Computer Society, p. 197-202 6 p. 7796112. (Proceedings of the Asian Test Symposium).

研究成果: Conference contribution

5 引文 斯高帕斯(Scopus)

Efficient probing schemes for fine-pitch pads of InFO wafer-level chip-scale package

Huang, Y. C., Lin, B. Y., Wu, C. W., Lee, M., Chen, H., Lin, H. C., Peng, C. N. & Wang, M. J., 2016 六月 5, Proceedings of the 53rd Annual Design Automation Conference, DAC 2016. Institute of Electrical and Electronics Engineers Inc., a58. (Proceedings - Design Automation Conference; 卷 05-09-June-2016).

研究成果: Conference contribution

1 引文 斯高帕斯(Scopus)

Exploration methodology for 3D memory redundancy architectures under redundancy constraints

Lin, B. Y., Lee, M. & Wu, C. W., 2013 一月 1, 於 : Proceedings of the Asian Test Symposium. p. 1-6 6 p., 6690605.

研究成果: Conference article

6 引文 斯高帕斯(Scopus)

Exploration Methodology for 3D Memory Redun- dancy Architectures under Redundancy Constraints

Wu, C-W., Lin, B-Y. & Lee, M., 2013 十一月, 22nd IEEE Asian Test Symp. (ATS). Yilan

研究成果: Conference contribution

Failure-Pattern-Based Test Data Compression for Memories

Wu, C-W., Lin, B-Y. & Lee, M., 2013 七月, VLSI Test Technology Workshop (VTTW). New Taipei City

研究成果: Conference contribution

Fault Models and Test Algorithms for Multi-Level Cell (MLC) Crossbar RRAM

Wu, C-W. & Hou, K-W., 2017 七月, VLSI Test Technology Workshop (VTTW). Nantou

研究成果: Conference contribution

Foreword

Wu, C. W., Lee, K. J., Wang, L. C. & Huang, S. Y., 2017 十一月 3, 於 : ITC-Asia 2017 - International Test Conference in Asia. p. iv 8097094.

研究成果: Editorial

Generalization of an enhanced ECC methodology for low power PSRAM

Chen, P. Y., Su, C. L., Chen, C. H. & Wu, C. W., 2013 六月 5, 於 : IEEE Transactions on Computers. 62, 7, p. 1318-1331 14 p., 6189334.

研究成果: Article

5 引文 斯高帕斯(Scopus)

Highly Reliable and Low-Cost Symbiotic IOT Devices and Systems

Wu, C-W., Lin, B-Y., Hung, H-W., Tseng, S-M. & Chen, C., 2017 十月, IEEE Int. Test Conf. (ITC). Fort Worth, Texas

研究成果: Conference contribution

3 引文 斯高帕斯(Scopus)

In-situ method for TSV delay testing and characterization using input sensitivity analysis

You, J. W., Huang, S. Y., Lin, Y. H., Tsai, M. H., Kwai, D. M., Chou, Y. F. & Wu, C. W., 2013 一月 1, 於 : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 21, 3, p. 443-453 11 p., 6166351.

研究成果: Article

23 引文 斯高帕斯(Scopus)

Large graph computing systems

Wu, C., Zhang, G., Li, K. & Zheng, W., 2017 一月 1, Big Data Management and Processing. CRC Press, p. 347-362 16 p.

研究成果: Chapter

Layout-Oriented Defect Set Reduction for Fast Circuit Simulation in Cell-Aware Test

Liu, H. W., Lin, B. Y. & Wu, C. W., 2016 十二月 22, Proceedings - 2016 IEEE 25th Asian Test Symposium, ATS 2016. IEEE Computer Society, p. 156-160 5 p. 7796105. (Proceedings of the Asian Test Symposium).

研究成果: Conference contribution

2 引文 斯高帕斯(Scopus)