尋找研究成果

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2019

A Self-Organizing Map-Based Adaptive Traffic Light Control System with Reinforcement Learning

Kao, Y. C. & Wu, C. W., 2019 二月 19, Conference Record of the 52nd Asilomar Conference on Signals, Systems and Computers, ACSSC 2018. Matthews, M. B. (編輯). IEEE Computer Society, p. 2060-2064 5 p. 8645125. (Conference Record - Asilomar Conference on Signals, Systems and Computers; 卷 2018-October).

研究成果: Conference contribution

Self organizing maps
Reinforcement learning
Telecommunication traffic
Control systems
Learning systems

Redio: Accelerating Disk-Based Graph Processing by Reducing Disk I/Os

Wu, C., Zhang, G., Wang, Y., Jiang, X. & Zheng, W., 2019 三月 1, 於 : IEEE Transactions on Computers. 68, 3, p. 414-425 12 p., 8489961.

研究成果: Article

Data storage equipment
Graph in graph theory
Processing
Scalability
Experiments

Solutions to Multiple Probing Challenges for Test Access to Multi-Die Stacked Integrated Circuits

Marinissen, E. J., Fodor, F., Podpod, A., Stucchi, M., Jian, Y. R. & Wu, C. W., 2019 一月 23, International Test Conference 2018, ITC 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 8624731. (Proceedings - International Test Conference; 卷 2018-October).

研究成果: Conference contribution

Integrated Circuits
Integrated circuits
Die
Probe
Wafer

The last byte: Baseball and testing

Wu, C. W., 2019 十二月, 於 : IEEE Design and Test. 36, 6, 1 p., 8844727.

研究成果: Comment/debate

2018

A Built-in Self-Test Scheme for Detecting Defects in FinFET-Based SRAM Circuit

Chen, M. C., Wu, T. H. & Wu, C. W., 2018 十二月 6, Proceedings - 2018 IEEE 27th Asian Test Symposium, ATS 2018. IEEE Computer Society, p. 19-24 6 p. 8567404. (Proceedings of the Asian Test Symposium; 卷 2018-October).

研究成果: Conference contribution

Built-in self test
Static random access storage
Defects
Networks (circuits)
Transistors

A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive Devices

Pan, Y-C., Jian, Y-R., Liu, H-H. & Wu, C-W., 2018 七月, VLSI Test Technology Workshop (VTTW). Nantou

研究成果: Conference contribution

An enhanced boundary scan architecture for inter-die interconnect leakage measurement in 2.5D and 3D packages

Law, P. M. P., Wu, C. W., Lin, L. Y. & Hong, H. C., 2018 一月 24, Proceedings - 2017 IEEE 26th Asian Test Symposium, ATS 2017. Taipei: IEEE Computer Society, p. 1-6 6 p. (Proceedings of the Asian Test Symposium).

研究成果: Conference contribution

Leakage currents
Packaging
Defects
Fans
Built-in self test

Automated Probe-Mark Analysis

Wu, C-W., Jian, Y-R., Fodor, F. & Marinissen, E. J., 2018 六月, Semiconductor Wafer Test Workshop (SWTW).

研究成果: Conference contribution

Covering hard-To-detect defects by thermal quorum sensing

Chuang, P. Y., Wu, C. W. & Chen, H. H., 2018 六月 29, Proceedings - 2018 23rd IEEE European Test Symposium, ETS 2018. Bremen: Institute of Electrical and Electronics Engineers Inc., p. 1-2 2 p. (Proceedings of the European Test Workshop; 卷 2018-May).

研究成果: Conference contribution

Defects
Networks (circuits)
Testing
Cells
Hot Temperature

RRAM-based neuromorphic hardware reliability improvement by self-healing and error correction

Hu, J. Y., Hou, K. W., Lo, C. Y., Chou, Y. F. & Wu, C. W., 2018 九月 11, Proceedings - 2nd IEEE International Test Conference in Asia, ITC-Asia 2018. Institute of Electrical and Electronics Engineers Inc., p. 19-24 6 p. 8462942. (Proceedings - 2nd IEEE International Test Conference in Asia, ITC-Asia 2018).

研究成果: Conference contribution

Error correction
Memristors
Neural networks
Hardware
Degradation

Symbiotic Controller Design Using a Memory-Based FSM Model

Kuo, S. F. & Wu, C. W., 2018 八月 10, Proceedings - 2018 IEEE 27th International Symposium on Industrial Electronics, ISIE 2018. Institute of Electrical and Electronics Engineers Inc., p. 874-879 6 p. 8433783. (IEEE International Symposium on Industrial Electronics; 卷 2018-June).

研究成果: Conference contribution

Data storage equipment
Controllers
Energy utilization
Costs
Telecommunication traffic
2017
2 引文 (Scopus)

A Built-Off Self-Repair Scheme for Channel-Based 3D Memories

Liu, H. H., Lin, B. Y., Wu, C. W., Chiang, W. T., Mincent, L., Lin, H. C., Peng, C. N. & Wang, M. J., 2017 八月 1, 於 : IEEE Transactions on Computers. 66, 8, p. 1293-1301 9 p., 7850958.

研究成果: Article

Repair
Data storage equipment
Dynamic random access storage
Redundancy
Die

Building a fault tolerant framework with deadline guarantee in big data stream computing environments

Sun, D., Zhang, G., Wu, C., Li, K. & Zheng, W., 2017 十一月, 於 : Journal of Computer and System Sciences. 89, p. 4-23 20 p.

研究成果: Article

Deadline
Fault tolerance
Data Streams
Fault-tolerant
Computing

Cell-Aware Test Generation Time Reduction by Using Switch-Level ATPG

Wu, C-W., Chuang, P-Y. & Chen, H. H., 2017 九月, IEEE Int. Test Conf. in Asia (ITC-A). Taipei

研究成果: Conference contribution

1 引文 (Scopus)

Controller architecture for low-power, low-latency DRAM with built-in cache

Liu, Z. Y., Shih, H. C., Lin, B. Y. & Wu, C. W., 2017 四月 1, 於 : IEEE Design and Test. 34, 2, p. 69-78 10 p., 7397924.

研究成果: Article

Dynamic random access storage
Controllers
Data storage equipment

Fault Models and Test Algorithms for Multi-Level Cell (MLC) Crossbar RRAM

Wu, C-W. & Hou, K-W., 2017 七月, VLSI Test Technology Workshop (VTTW). Nantou

研究成果: Conference contribution

Foreword

Wu, C. W., Lee, K. J., Wang, L. C. & Huang, S. Y., 2017 十一月 3, 於 : ITC-Asia 2017 - International Test Conference in Asia. p. iv 8097094.

研究成果: Editorial

3 引文 (Scopus)

Highly Reliable and Low-Cost Symbiotic IOT Devices and Systems

Wu, C-W., Lin, B-Y., Hung, H-W., Tseng, S-M. & Chen, C., 2017 十月, IEEE Int. Test Conf. (ITC). Fort Worth, Texas

研究成果: Conference contribution

Large graph computing systems

Wu, C., Zhang, G., Li, K. & Zheng, W., 2017 一月 1, Big Data Management and Processing. CRC Press, p. 347-362 16 p.

研究成果: Chapter

Computer systems
Data storage equipment
Websites
Proteins
Big data

Symbiotic system models for efficient IGT system design and test

Wu, C. W., Lin, B. Y., Hung, H. W., Tseng, S. M. & Chen, C., 2017 十一月 3, ITC-Asia 2017 - International Test Conference in Asia. Institute of Electrical and Electronics Engineers Inc., p. 71-76 6 p. 8097114. (ITC-Asia 2017 - International Test Conference in Asia).

研究成果: Conference contribution

Insulated gate bipolar transistors (IGBT)
Systems analysis
Energy utilization
Costs
Repair

Symbiotic System Models for Efficient IOT System Design and Test

Wu, C-W., Chen, C., Lin, B-Y., Hung, H-W. & Tseng, S-M., 2017 九月, IEEE Int. Test Conf. in Asia (ITC-A). Taipei

研究成果: Conference contribution

3 引文 (Scopus)

Test Cost Reduction Methodology for InFO Wafer-Level Chip-Scale Package

Wang, K. L., Lin, B. Y., Wu, C. W., Lee, M., Chen, H., Lin, H. C., Peng, C. N. & Wang, M. J., 2017 六月 1, 於 : IEEE Design and Test. 34, 3, p. 50-58 9 p., 7464303.

研究成果: Article

Chip scale packages
Cost reduction
Packaging
Fans
Costs
2016
2 引文 (Scopus)

A fast sweep-line-based failure pattern extractor for memory diagnosis

Wei, S. Y., Lin, B. Y. & Wu, C. W., 2016 七月 22, Proceedings - 2016 21st IEEE European Test Symposium, ETS 2016. Institute of Electrical and Electronics Engineers Inc., 7519314. (Proceedings of the European Test Workshop; 卷 2016-July).

研究成果: Conference contribution

Data storage equipment
Product development
Experiments
3 引文 (Scopus)

A local parallel search approach for memory failure pattern identification

Lin, B. Y., Wu, C. W., Lee, M., Lin, H. C., Peng, C. N. & Wang, M. J., 2016 三月 1, 於 : IEEE Transactions on Computers. 65, 3, p. 770-780 11 p., 7173026.

研究成果: Article

Data storage equipment
Logic circuits
Logic
Failure Analysis
Design Rules
1 引文 (Scopus)

Configurable Cubical Redundancy Schemes for Channel-Based 3-D DRAM Yield Improvement

Lin, B. Y., Chiang, W. T., Wu, C. W., Lee, M., Lin, H. C., Peng, C. N. & Wang, M. J., 2016 四月 1, 於 : IEEE Design and Test. 33, 2, p. 30-39 10 p., 7154435.

研究成果: Article

Dynamic random access storage
Redundancy
Data storage equipment
4 引文 (Scopus)

Efficient Cell-Aware Fault Modeling by Switch-Level Test Generation

Chen, H. H., Chen, S. Y. H., Chuang, P. Y. & Wu, C. W., 2016 十二月 22, Proceedings - 2016 IEEE 25th Asian Test Symposium, ATS 2016. IEEE Computer Society, p. 197-202 6 p. 7796112. (Proceedings of the Asian Test Symposium).

研究成果: Conference contribution

Transistors
Switches
Defects
Circuit simulation
Electric network analysis
1 引文 (Scopus)

Efficient probing schemes for fine-pitch pads of InFO wafer-level chip-scale package

Huang, Y. C., Lin, B. Y., Wu, C. W., Lee, M., Chen, H., Lin, H. C., Peng, C. N. & Wang, M. J., 2016 六月 5, Proceedings of the 53rd Annual Design Automation Conference, DAC 2016. Institute of Electrical and Electronics Engineers Inc., a58. (Proceedings - Design Automation Conference; 卷 05-09-June-2016).

研究成果: Conference contribution

Chip scale packages
Wafer
Fans
Packaging
Chip
2 引文 (Scopus)

Layout-Oriented Defect Set Reduction for Fast Circuit Simulation in Cell-Aware Test

Liu, H. W., Lin, B. Y. & Wu, C. W., 2016 十二月 22, Proceedings - 2016 IEEE 25th Asian Test Symposium, ATS 2016. IEEE Computer Society, p. 156-160 5 p. 7796105. (Proceedings of the Asian Test Symposium).

研究成果: Conference contribution

Circuit simulation
Defects
Transistors
Resistors
Capacitors
Phase change memory
Computer architecture
Computer systems
Data storage equipment
Dynamic random access storage

Symbiotic-System Approach for IOT Devices

Wu, C-W., 2016 十一月, 25th IEEE Asian Test Symp. (ATS), Hiroshima. Hiroshima

研究成果: Conference contribution

2015
2 引文 (Scopus)

A Computer Designed Half Gb 16-Channel 819Gb/s High-Bandwidth and 10ns Low-Latency DRAM for 3D Stacked Memory Devices Using TSVs

Wu, C-W., Luo, P-W., Chen, C-K., Sung, Y-H., Wu, W., Shih, H-C., Lee, C-H., Lee, K-H., Li, M-W., Lung, M-C., Lu, C-N., Chou, Y-F., Shih, P-L., Ke, C-H., Shiah, C., Stolt, P., Tomishima, S., Kwai, D-M., Rong, B-D., Lu, N. 及其他1, Lu, S-L., 2015 六月, IEEE Symp. VLSI Circuits (VLSI).

研究成果: Conference contribution

1 引文 (Scopus)

Redundancy architectures for channel-based 3D DRAM yield improvement

Lin, B. Y., Chiang, W. T., Wu, C. W., Lee, M., Lin, H. C., Peng, C. N. & Wang, M. J., 2015 二月 6, Proceedings - 2014 IEEE International Test Conference, ITC 2014. Seattle, Washington: Institute of Electrical and Electronics Engineers Inc., 7035331. (Proceedings - International Test Conference; 卷 2015-February).

研究成果: Conference contribution

Random Access
Redundancy
Die
Data storage equipment
Logic
41 引文 (Scopus)

RRAM defect modeling and failure analysis based on march test and a novel squeeze-search scheme

Chen, C. Y., Shih, H. C., Wu, C. W., Lin, C. H., Chiu, P. F., Sheu, S. S. & Chen, F. T., 2015 一月 1, 於 : IEEE Transactions on Computers. 64, 1, p. 180-190 11 p., 6725492.

研究成果: Article

Failure Analysis
Random Access
Failure analysis
Defects
Data storage equipment

System-level test coverage prediction by structural stress test data mining

Lin, B. Y., Wu, C. W. & Chen, H. H., 2015 五月 28, 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015. Institute of Electrical and Electronics Engineers Inc., 7114508. (2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015).

研究成果: Conference contribution

Program processors
Data mining
Learning systems
Silicon
Electric potential
2014
5 引文 (Scopus)

Application-independent testing of 3-D field programmable gate array interconnect faults

Peng, Y. L., Kwai, D. M., Chou, Y. F. & Wu, C. W., 2014 二月 1, 於 : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 22, 2, p. 207-219 13 p., 6459051.

研究成果: Article

Field programmable gate arrays (FPGA)
Testing
Silicon
Scalability
Switches
1 引文 (Scopus)

BIST-assisted tuning scheme for minimizing io-channel power of TSV-based 3D DRAMs

Yu, Y. C., Yang, C. C., Li, J. F., Lo, C. Y., Chen, C. H., Lai, J. S., Kwai, D. M., Chou, Y. F. & Wu, C. W., 2014 十二月 7, Proceedings - 23rd Asian Test Symposium, ATS 2014. Hsinchu: IEEE Computer Society, p. 1-6 6 p. 06979068. (Proceedings of the Asian Test Symposium).

研究成果: Conference contribution

Built-in self test
Dynamic random access storage
Tuning
Silicon
Data storage equipment
10 引文 (Scopus)

DArT: A component-based DRAM area, power, and timing modeling tool

Shih, H. C., Luo, P. W., Yeh, J. C., Lin, S. Y., Kwai, D. M., Lu, S. L., Schaefer, A. & Wu, C. W., 2014 一月 1, 於 : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 33, 9, p. 1356-1369 14 p., 6879579.

研究成果: Article

Dynamic random access storage
Circuit simulation
Bandwidth

DRAM system simulation speed-Up by effective-cycle selection

Chiang, H. C., Wang, M. Y. & Wu, C. W., 2014 一月 1, Proceedings - 2014 International Symposium on Computer, Consumer and Control, IS3C 2014. IEEE Computer Society, p. 1053-1056 4 p. 6846067. (Proceedings - 2014 International Symposium on Computer, Consumer and Control, IS3C 2014).

研究成果: Conference contribution

Dynamic random access storage
Redundancy
Data storage equipment
Simulators
Systems analysis
5 引文 (Scopus)

Low-cost post-bond testing of 3-D ICs containing a passive silicon interposer base

Chi, C. C., Marinissen, E. J., Goel, S. K. & Wu, C. W., 2014 十一月 1, 於 : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 22, 11, p. 2388-2401 14 p., 6680768.

研究成果: Article

Silicon
Testing
Costs
Wire
Cost benefit analysis
3 引文 (Scopus)

On improving interconnect defect diagnosis resolution and yield for interposer-based 3-D ICs

Chi, C. C., Lin, B. Y., Wu, C. W., Wang, M. J., Lin, H. C. & Peng, C. N., 2014 一月 1, 於 : IEEE Design and Test. 31, 4, p. 16-26 11 p., 6221038.

研究成果: Article

Built-in self test
Defects
PROM
Flash memory
Clocks
2013
32 引文 (Scopus)

3D-IC interconnect test, diagnosis, and repair

Chi, C. C., Wu, C. W., Wang, M. J. & Lin, H. C., 2013 八月 14, Proceedings - 2013 IEEE 31st VLSI Test Symposium, VTS 2013. 6548905. (Proceedings of the IEEE VLSI Test Symposium).

研究成果: Conference contribution

Repair
Defects
Cost benefit analysis
Profitability
Silicon
19 引文 (Scopus)

A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS

Lin, T. J., Chien, C. A., Chang, P. Y., Chen, C. W., Wang, P. H., Shyu, T. Y., Chou, C. Y., Luo, S. C., Guo, J. I., Chen, T. F., Chuang, G. C. H., Chu, Y. H., Cheng, L. C., Su, H. M., Jou, C., Ieong, M., Wu, C. W. & Wang, J. S., 2013 四月 29, 2013 IEEE International Solid-State Circuits Conference, ISSCC 2013 - Digest of Technical Papers. p. 158-159 2 p. 6487680. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; 卷 56).

研究成果: Conference contribution

Video recording
Static random access storage
ROM
Pixels
Macros
2 引文 (Scopus)

AC-plus scan methodology for small delay testing and characterization

Li, T. Y., Huang, S. Y., Hsu, H. J., Tzeng, C. W., Huang, C. T., Liou, J. J., Ma, H. P., Huang, P. C., Bor, J. C., Tien, C. C., Wang, C. H. & Wu, C. W., 2013 一月 1, 於 : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 21, 2, p. 329-341 13 p., 6166352.

研究成果: Article

Defects
Testing
Flip flop circuits
Phase locked loops
Clocks
5 引文 (Scopus)

A hybrid ECC and redundancy technique for reducing refresh power of DRAMs

Yu, Y. C., Hou, C. S., Chang, L. J., Li, J. F., Lo, C. Y., Kwai, D. M., Chou, Y. F. & Wu, C. W., 2013 八月 14, Proceedings - 2013 IEEE 31st VLSI Test Symposium, VTS 2013. 6548927. (Proceedings of the IEEE VLSI Test Symposium).

研究成果: Conference contribution

Dynamic random access storage
Redundancy
Data storage equipment
Networks (circuits)
Error correction
1 引文 (Scopus)

Analytical modeling and numerical simulations of temperature field in TSV-based 3D ICs

Shiyanovskii, Y., Papachristou, C. & Wu, C. W., 2013 七月 5, Proceedings of the 14th International Symposium on Quality Electronic Design, ISQED 2013. p. 24-29 6 p. 6523585. (Proceedings - International Symposium on Quality Electronic Design, ISQED).

研究成果: Conference contribution

Temperature distribution
Silicon
Computer simulation
Electric heating
Heat transfer
2 引文 (Scopus)

An enhanced double-TSV Scheme for defect tolerance in 3D-IC

Shih, H. C. & Wu, C. W., 2013 十月 21, Proceedings - Design, Automation and Test in Europe, DATE 2013. p. 1486-1489 4 p. 6513748. (Proceedings -Design, Automation and Test in Europe, DATE).

研究成果: Conference contribution

Silicon
Defects
Electric fuses
Repair
Electric power utilization
10 引文 (Scopus)

An FPGA-based test platform for analyzing data retention time distribution of DRAMs

Hou, C. S., Li, J. F., Lo, C. Y., Kwai, D. M., Chou, Y. F. & Wu, C. W., 2013 八月 15, 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013. 6533853. (2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013).

研究成果: Conference contribution

Dynamic random access storage
Field programmable gate arrays (FPGA)
Data storage equipment
Electric potential
Temperature
5 引文 (Scopus)

Exploration methodology for 3D memory redundancy architectures under redundancy constraints

Lin, B. Y., Lee, M. & Wu, C. W., 2013 一月 1, 於 : Proceedings of the Asian Test Symposium. p. 1-6 6 p., 6690605.

研究成果: Conference article

Redundancy
Data storage equipment
Repair
Memory architecture

Exploration Methodology for 3D Memory Redun- dancy Architectures under Redundancy Constraints

Wu, C-W., Lin, B-Y. & Lee, M., 2013 十一月, 22nd IEEE Asian Test Symp. (ATS). Yilan

研究成果: Conference contribution