摘要
A wide bandwidth Σ-Δ modulation based analog built-in self-test (BIST) system that can diagnose the prototype is presented. It consists of a low-cost design-for-testability (DfT) switched-capacitor filter as the circuit under test (CUT) and a wide bandwidth analog response extractor (ARE) to digitize the analog responses for final DSP analysis. The first stage of the DfT CUT is reconfigured to accept a repetitive Σ-Δ modulated bit-steam as its stimulus. This DfT technique reuses every original component and thus provides the advantages of lowering the testing cost, increasing the fault coverage as well as the accuracy, and being able to perform the at-speed tests. The ARE is a cascaded 2-1-1-1 fifth-order Σ-Δ modulator equipped with single-bit quantizers to extend the testing bandwidth while retaining moderate tolerance of circuit imperfections. Our measurement results show that this ARE is able to provide a -95 dB spurious free dynamic range over 1 MHz bandwidth when operates at 30 MHz. A multi-tone test is performed to manifest the wide bandwidth and high accuracy of our BIST system. Based on the BIST results, a novel method of diagnosing the prototype to speed up the time-to-market is also proposed and demonstrated by our BIST system.
| 原文 | English |
|---|---|
| 頁(從 - 到) | 62-67 |
| 頁數 | 6 |
| 期刊 | Proceedings of the Asian Test Symposium |
| 出版狀態 | Published - 2004 12月 1 |
| 事件 | Proceedings of the Asian Test Symposium, ATS'04 - Kenting, Taiwan 持續時間: 2004 11月 15 → 2004 11月 17 |
All Science Journal Classification (ASJC) codes
- 電氣與電子工程
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