A 0.07-mm2162-mW DAC Achieving >65 dBc SFDR and < -70 dBc IM3 at 10 GS/s with Output Impedance Compensation and Concentric Parallelogram Routing

Hung Yi Huang, Tai Haur Kuo

研究成果: Article同行評審

摘要

A digital-to-analog converter (DAC) with small-size non-cascoded current cells is proposed to achieve small area, low-power consumption, and high linearity over a wide bandwidth. An output impedance compensation (OIC) technique using a compensation resistor, implemented by a PMOS with code-dependent gate voltage control, is proposed to remedy the nonlinearity induced by the insufficient output impedance of the non-cascoded current cells. In addition, a proposed concentric parallelogram routing (CPR) technique, in which the subcells of each current cell are arranged such that they form a parallelogram shape with a common centroid, is used to reduce both the mismatch error and the routing-induced timing skew among the current cells. The DAC, implemented in a 28-nm CMOS process, achieves >65-dBc spurious-free dynamic range (SFDR) and < -70-dBc third-order intermodulation distortion (IM3) over the entire Nyquist bandwidth at 10 GS/s while consuming 162 mW from a single 1.1 V supply.

原文English
文章編號9098055
頁(從 - 到)2478-2488
頁數11
期刊IEEE Journal of Solid-State Circuits
55
發行號9
DOIs
出版狀態Published - 2020 九月

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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