A 0.07mm2 210mW Single-1.1V-Supply 14-bit 10GS/s DAC with Concentric Parallelogram Routing and Output Impedance Compensation

Hung-yi Huang, Tai-haur Kuo

研究成果: Paper

原文English
頁面C136-C137
DOIs
出版狀態Published - 2019 六月
事件2019 Symposium on VLSI Circuits - Kyoto, Japan
持續時間: 2019 六月 92019 六月 14

Conference

Conference2019 Symposium on VLSI Circuits
期間19-06-0919-06-14

引用此文

@conference{1b987caa7fbc48c199bb7e808ebc1025,
title = "A 0.07mm2 210mW Single-1.1V-Supply 14-bit 10GS/s DAC with Concentric Parallelogram Routing and Output Impedance Compensation",
author = "Hung-yi Huang and Tai-haur Kuo",
year = "2019",
month = "6",
doi = "10.23919/VLSIC.2019.8778067",
language = "English",
pages = "C136--C137",
note = "2019 Symposium on VLSI Circuits ; Conference date: 09-06-2019 Through 14-06-2019",

}

A 0.07mm2 210mW Single-1.1V-Supply 14-bit 10GS/s DAC with Concentric Parallelogram Routing and Output Impedance Compensation. / Huang, Hung-yi; Kuo, Tai-haur.

2019. C136-C137 論文發表於 2019 Symposium on VLSI Circuits, .

研究成果: Paper

TY - CONF

T1 - A 0.07mm2 210mW Single-1.1V-Supply 14-bit 10GS/s DAC with Concentric Parallelogram Routing and Output Impedance Compensation

AU - Huang, Hung-yi

AU - Kuo, Tai-haur

PY - 2019/6

Y1 - 2019/6

U2 - 10.23919/VLSIC.2019.8778067

DO - 10.23919/VLSIC.2019.8778067

M3 - Paper

SP - C136-C137

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