A DAC with small-size non-cascoded current cells is proposed to achieve small area, low power, high linearity, and wide bandwidth. The proposed concentric parallelogram routing (CPR) reduces mismatch and timing skew among cells. In addition, the proposed output impedance compensation (OIC) remedies the insufficient output impedance of the noncascoded current cells. The DAC, implemented in 28nm CMOS process, achieves \gt64 dB SFDR over the entire Nyquist bandwidth at 10GS/s while consuming 210mW from a single 1.1V supply. Compared with other state-of-the-art CMOS DACs with resolutions higher than 10bit and Nyquist bandwidths over 3.4GHz, this DAC has an active area of only 0.07mm2 less than 1/12 of the others and the best performance for a commonly-used figure-of-merit (FoM).