A 0.25-μm 20-dBm 2.4-GHz CMOS power amplifier with an integrated diode linearizer

Cheng Chi Yen; Huey Ru Chuang

doi:10.1109/LMWC.2003.808722

A 0.25-μm 20-dBm 2.4-GHz CMOS power amplifier with an integrated diode linearizer

Cheng Chi Yen, Huey Ru Chuang

電腦與通信工程研究所

研究成果: Letter › 同行評審

75 引文斯高帕斯（Scopus）

摘要

A 2.4-GHz CMOS power amplifier (PA) with an output power 20 dBm using 0.25-μm 1P5M standard CMOS process is presented. The PA uses an integrated diode connected NMOS transistor as the function of diode linearizer. It is believed that this is firstly reported to use the diode linearization technique in CMOS PA design. It shows effectively improvement in linearity from gain compression and ACPR measured results. Measurements are performed by using a FR-4 PCB test fixture. The fabricated power amplifier exhibits an output power of 20 dBm and a power-added efficiency as high as 28%. The obtained PA performances demonstrate the standard CMOS process potentialities for medium power RF amplification at 2.4 GHz wireless communication band.

原文	English
頁（從 - 到）	45-47
頁數	3
期刊	IEEE Microwave and Wireless Components Letters
卷	13
發行號	2
DOIs	https://doi.org/10.1109/LMWC.2003.808722
出版狀態	Published - 2003 2月

All Science Journal Classification (ASJC) codes

凝聚態物理學
電氣與電子工程

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10.1109/LMWC.2003.808722

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引用此

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title = "A 0.25-μm 20-dBm 2.4-GHz CMOS power amplifier with an integrated diode linearizer",

abstract = "A 2.4-GHz CMOS power amplifier (PA) with an output power 20 dBm using 0.25-μm 1P5M standard CMOS process is presented. The PA uses an integrated diode connected NMOS transistor as the function of diode linearizer. It is believed that this is firstly reported to use the diode linearization technique in CMOS PA design. It shows effectively improvement in linearity from gain compression and ACPR measured results. Measurements are performed by using a FR-4 PCB test fixture. The fabricated power amplifier exhibits an output power of 20 dBm and a power-added efficiency as high as 28%. The obtained PA performances demonstrate the standard CMOS process potentialities for medium power RF amplification at 2.4 GHz wireless communication band.",

author = "Yen, {Cheng Chi} and Chuang, {Huey Ru}",

note = "Funding Information: Manuscript received April 4, 2002; revised July 30, 2002. This work was supported by the National Science Council, Taiwan, R.O.C., under Grant NSC 90-2213-E-006-055. The review of this letter was arranged by Associate Editor Dr. Arvind Sharma.",

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N2 - A 2.4-GHz CMOS power amplifier (PA) with an output power 20 dBm using 0.25-μm 1P5M standard CMOS process is presented. The PA uses an integrated diode connected NMOS transistor as the function of diode linearizer. It is believed that this is firstly reported to use the diode linearization technique in CMOS PA design. It shows effectively improvement in linearity from gain compression and ACPR measured results. Measurements are performed by using a FR-4 PCB test fixture. The fabricated power amplifier exhibits an output power of 20 dBm and a power-added efficiency as high as 28%. The obtained PA performances demonstrate the standard CMOS process potentialities for medium power RF amplification at 2.4 GHz wireless communication band.

AB - A 2.4-GHz CMOS power amplifier (PA) with an output power 20 dBm using 0.25-μm 1P5M standard CMOS process is presented. The PA uses an integrated diode connected NMOS transistor as the function of diode linearizer. It is believed that this is firstly reported to use the diode linearization technique in CMOS PA design. It shows effectively improvement in linearity from gain compression and ACPR measured results. Measurements are performed by using a FR-4 PCB test fixture. The fabricated power amplifier exhibits an output power of 20 dBm and a power-added efficiency as high as 28%. The obtained PA performances demonstrate the standard CMOS process potentialities for medium power RF amplification at 2.4 GHz wireless communication band.

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A 0.25-μm 20-dBm 2.4-GHz CMOS power amplifier with an integrated diode linearizer

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