A 0.25-μm 20-dBm 2.4-GHz CMOS power amplifier with an integrated diode linearizer

Cheng Chi Yen, Huey Ru Chuang

研究成果: Letter同行評審

72 引文 斯高帕斯(Scopus)

摘要

A 2.4-GHz CMOS power amplifier (PA) with an output power 20 dBm using 0.25-μm 1P5M standard CMOS process is presented. The PA uses an integrated diode connected NMOS transistor as the function of diode linearizer. It is believed that this is firstly reported to use the diode linearization technique in CMOS PA design. It shows effectively improvement in linearity from gain compression and ACPR measured results. Measurements are performed by using a FR-4 PCB test fixture. The fabricated power amplifier exhibits an output power of 20 dBm and a power-added efficiency as high as 28%. The obtained PA performances demonstrate the standard CMOS process potentialities for medium power RF amplification at 2.4 GHz wireless communication band.

原文English
頁(從 - 到)45-47
頁數3
期刊IEEE Microwave and Wireless Components Letters
13
發行號2
DOIs
出版狀態Published - 2003 二月

All Science Journal Classification (ASJC) codes

  • 凝聚態物理學
  • 電氣與電子工程

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