A 0.35-1 V 0.2-3 GS/s 4-bit low-power flash ADC for a solar-powered wireless module

Ying Z. Lin, Yu Chang Lien, Soon-Jyh Chang

研究成果: Conference contribution

5 引文 斯高帕斯(Scopus)

摘要

This paper reports a 4-bit flash ADC with a supply range from 0.35 to 1 V. The corresponding sampling rates are 0.2 to 3 GS/s. This low-voltage low-power ADC is a feasible building block for a solar-powered wireless module. Passive subtraction by resistor ladders replaces active subtraction by 4-input preamplifiers since the linearity of ladders is independent of supply voltage. Passive subtraction and low-threshold devices enable low-supply operation. At 1.2 GS/s, the ADC consumes 1.93 mW from a 0.6-V supply. The ENOB is 3.60 bit and ERBW is 550 MHz, resulting in an FOM of 145 fJ/conversion-step.

原文English
主出版物標題Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010
頁面299-302
頁數4
DOIs
出版狀態Published - 2010 十一月 8
事件2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010 - Hsin Chu, Taiwan
持續時間: 2010 四月 262010 四月 29

出版系列

名字Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010

Other

Other2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010
國家/地區Taiwan
城市Hsin Chu
期間10-04-2610-04-29

All Science Journal Classification (ASJC) codes

  • 硬體和架構
  • 電氣與電子工程

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