A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS

Tay Jyi Lin, Cheng An Chien, Pei Yao Chang, Ching Wen Chen, Po Hao Wang, Ting Yu Shyu, Chien Yung Chou, Shien Chun Luo, Jiun In Guo, Tien Fu Chen, Gene C.H. Chuang, Yuan Hua Chu, Liang Chia Cheng, Hong Men Su, Chewnpu Jou, Meikei Ieong, Cheng Wen Wu, Jinn Shyan Wang

研究成果: Conference contribution

19 引文 斯高帕斯(Scopus)

摘要

This paper presents a video recording SoC fabricated in 65nm low-power technology, which integrates a complexity and bandwidth-effective H.264 encoder, an ultra-low-power (ULP) MPU, with timing-optimized ROM and 8T SRAM macros for ultra-low-voltage (ULV) operation, a 512Kb ULV and leakage-aware 8T SRAM for the frame buffer (FB), and various on-chip peripherals, such as external memory interfaces (Fig. 9.3.1). Utilizing ULV cell libraries with custom-pulsed D flip-flops (PFF) for wide-range voltage scaling, ROM/SRAM macros optimized simultaneously for timing and leakage, and advanced energy management (AEM), the SoC achieves 32fps HD720 H.264 encoding at 1.0V, down to 0.57nJ/pixel ultra-low energy dissipation at 0.48V (30fps QQVGA H.264 encoding for preview through ANT+).

原文English
主出版物標題2013 IEEE International Solid-State Circuits Conference, ISSCC 2013 - Digest of Technical Papers
頁面158-159
頁數2
DOIs
出版狀態Published - 2013 四月 29
事件2013 60th IEEE International Solid-State Circuits Conference, ISSCC 2013 - San Francisco, CA, United States
持續時間: 2013 二月 172013 二月 21

出版系列

名字Digest of Technical Papers - IEEE International Solid-State Circuits Conference
56
ISSN(列印)0193-6530

Other

Other2013 60th IEEE International Solid-State Circuits Conference, ISSCC 2013
國家United States
城市San Francisco, CA
期間13-02-1713-02-21

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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    Lin, T. J., Chien, C. A., Chang, P. Y., Chen, C. W., Wang, P. H., Shyu, T. Y., Chou, C. Y., Luo, S. C., Guo, J. I., Chen, T. F., Chuang, G. C. H., Chu, Y. H., Cheng, L. C., Su, H. M., Jou, C., Ieong, M., Wu, C. W., & Wang, J. S. (2013). A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS. 於 2013 IEEE International Solid-State Circuits Conference, ISSCC 2013 - Digest of Technical Papers (頁 158-159). [6487680] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; 卷 56). https://doi.org/10.1109/ISSCC.2013.6487680