A 0.5-TO-4 GBPS continuous-rate clock and data recovery circuit with bidirectional frequency detection

Yen Long Lee, Yen Chi Chen, Soon Jyh Chang, Yu Po Cheng

研究成果: Article

1 引文 斯高帕斯(Scopus)

摘要

This paper presents a continuous-rate clock and data recovery circuit with bidirectional frequency detection. The proposed frequency detection mechanism skillfully combines rotational frequency detector and sub-harmonic tone detection techniques. By doing this, this clock and data recovery circuit achieves no locking range limitation and provides automatically bidirectional frequency detection characteristic. Based on the proposed frequency detection methodology, a proof-of-concept clock and data recovery circuit is implemented to demonstrate the feasibility and effectiveness of the proposed design. The CDR circuit is fabricated in a TSMC 0.18-μm CMOS process. The core area is 0.137 mm2. The power consumption of this CDR circuit is 132.1 mW for a supply of 1.8V when input data rate is 4 Gbps. The measured peak-to-peak jitter and rms jitter of the recovered clock are 92.5 ps and 17.3 ps for a 4-Gbps 27-l PRBS, respectively. Moreover, the measured peak-to-peak jitter and rms jitter of the recovered clock are 90.9 ps and 16.9 ps for a 0.5-Gb/s 27-l PRBS, respectively.

原文English
頁(從 - 到)243-252
頁數10
期刊International Journal of Electrical Engineering
21
發行號6
DOIs
出版狀態Published - 2014 十二月 1

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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