A 0.8-V 250-MSample/s double-sampled inverse-flip-around sample-and-hold circuit based on switched-opamp architecture

Hsin Hung Ou, Bin Da Liu, Soon Jyh Chang

研究成果: Article

3 引文 斯高帕斯(Scopus)

摘要

This paper proposes a low-voltage high-speed sample-and-hold (S/H) structure with excellent power efficiency. Based on the switched-opamp technique, an inverse-flip-around architecture which maximizes the feedback factor is employed in the proposed S/H. A skew-insensitive double-sampling mechanism is presented to increase the throughput by a factor of two while eliminating the timing mismatch associated with double-sampling circuits. Furthermore, a dual-input dual-output opamp is proposed to incorporate double-sampling into the switched-opamp based S/H. This opamp also removes the memory effect in double-sampling circuitry and features fast turn-on time to improve the speed performance in switched-opamp circuits. Simulation results using a 0.13-μm CMOS process model demonstrates the proposed S/H circuit has a total-harmonic-distortion of -67.3dB up to 250MSample/s and a 0.8V PP input range at 0.8V supply. The power consumption is 3.5mW and the figure-of-merit is only 7.4fJ/step.

原文English
頁(從 - 到)1480-1487
頁數8
期刊IEICE Transactions on Electronics
E91-C
發行號9
DOIs
出版狀態Published - 2008 九月

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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