A 0.8 V switched-opamp bandpass ΔΣ modulator using a two-path architecture

Hsiang Hui Chang, Shang Ping Chen, Kuang-Wei Cheng, Shen Iuan Liu

研究成果: Conference contribution

2 引文 斯高帕斯(Scopus)

摘要

In this paper, a very low-voltage fourth-order bandpass delta-sigma modulator with a two-path architecture is presented. Using the modified switched opamp technique enables the modulator to operate at only 0.8 V supply voltage without any voltage multiplier or bootstrapping switch. Realized in a 0.25 μm 1P5M standard CMOS process, the prototype modulator exhibits a signal-to-noise-plus-distortion ratio (SNDR) of 60.6 db and a dynamic range (DR) of 68 db in a 30 kHz signal bandwidth centered at 1.25 MHz while consuming 2.5 mW and occupying an active area of 2.11 mm2.

原文English
主出版物標題2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings
發行者Institute of Electrical and Electronics Engineers Inc.
頁面1-4
頁數4
ISBN(電子)0780373634, 9780780373631
DOIs
出版狀態Published - 2002 一月 1
事件3rd IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Taipei, Taiwan
持續時間: 2002 八月 62002 八月 8

出版系列

名字2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings

Other

Other3rd IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002
國家/地區Taiwan
城市Taipei
期間02-08-0602-08-08

All Science Journal Classification (ASJC) codes

  • 硬體和架構
  • 電氣與電子工程

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