A 0.9-V 11-bit 25-MS/s binary-search SAR ADC in 90-nm CMOS

Ying Zu Lin, Soon-Jyh Chang, Ya Ting Shyu, Guan Ying Huang, Chun Cheng Liu

研究成果: Conference contribution

14 引文 斯高帕斯(Scopus)

摘要

This paper presents a new subrange analog-to-digital converter (ADC): a binary-search coarse ADC + a SAR fine ADC. The binary-search ADC improves conversion speed and gives coarse capacitors longer settling time. This ADC uses an RC hybrid DAC to reduce the unit capacitor count by 2. The rotation function of coarse capacitors enhances capacitor array linearity. The prototype in 90-nm CMOS only occupies an active area of 0.06 mm 2. From a 0.9-V supply, the power consumption is 0.32 and 0.58 mW at 10 and 25 MS/s, respectively. At 10 MS/s, the peak ENOB is 10.2 bit. At 25 MS/s, the peak ENOB is 9.9 bit and FOM is 29 fJ/conversion-step.

原文English
主出版物標題2011 Proceedings of Technical Papers
主出版物子標題IEEE Asian Solid-State Circuits Conference 2011, A-SSCC 2011
頁面69-72
頁數4
DOIs
出版狀態Published - 2011 十二月 1
事件7th IEEE Asian Solid-State Circuits Conference, A-SSCC 2011 - Jeju, Korea, Republic of
持續時間: 2011 十一月 142011 十一月 16

出版系列

名字2011 Proceedings of Technical Papers: IEEE Asian Solid-State Circuits Conference 2011, A-SSCC 2011

Other

Other7th IEEE Asian Solid-State Circuits Conference, A-SSCC 2011
國家Korea, Republic of
城市Jeju
期間11-11-1411-11-16

    指紋

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

引用此

Lin, Y. Z., Chang, S-J., Shyu, Y. T., Huang, G. Y., & Liu, C. C. (2011). A 0.9-V 11-bit 25-MS/s binary-search SAR ADC in 90-nm CMOS. 於 2011 Proceedings of Technical Papers: IEEE Asian Solid-State Circuits Conference 2011, A-SSCC 2011 (頁 69-72). [6123606] (2011 Proceedings of Technical Papers: IEEE Asian Solid-State Circuits Conference 2011, A-SSCC 2011). https://doi.org/10.1109/ASSCC.2011.6123606