A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13uμm CMOS process

Chun Cheng Liu, Soon-Jyh Chang, Guan Ying Huang, Yin Zu Lin

研究成果: Conference contribution

100 引文 斯高帕斯(Scopus)

摘要

This paper reports a 10-bit 50MS/s SAR ADC with a set-and-down capacitor switching method. Compared to the conventional method, the average switching energy is reduced about 81%. At 50MS/s and 1.2V supply, the ADC consumes 0.92mW and achieves an SNDR of 52.78dB, resulting in an FOM of 52fJ/Conversion-step. Fabricated in a 0.13uμm 1P8M CMOS technology, the ADC only occupies 0.075mm2 active area.

原文English
主出版物標題2009 Symposium on VLSI Circuits
頁面236-237
頁數2
出版狀態Published - 2009
事件2009 Symposium on VLSI Circuits - Kyoto, Japan
持續時間: 2009 六月 162009 六月 18

Other

Other2009 Symposium on VLSI Circuits
國家Japan
城市Kyoto
期間09-06-1609-06-18

    指紋

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

引用此

Liu, C. C., Chang, S-J., Huang, G. Y., & Lin, Y. Z. (2009). A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13uμm CMOS process. 於 2009 Symposium on VLSI Circuits (頁 236-237). [5205343]