A 1-μW 10-bit 200-kS/s SAR ADC with a bypass window for biomedical applications

Guan Ying Huang, Soon Jyh Chang, Chun Cheng Liu, Ying Zu Lin

研究成果: Article同行評審

101 引文 斯高帕斯(Scopus)

摘要

This paper presents an energy efficient successive-approximation-register (SAR) analog-to-digital converter (ADC) for biomedical applications. To reduce energy consumption, a bypass window technique is used to select switching sequences to skip several conversion steps when the signal is within a predefined small window. The power consumptions of the capacitive digital-to-analog converter (DAC), latch comparator, and digital control circuit of the proposed ADC are lower than those of a conventional SAR ADC. The proposed bypass window tolerates the DAC settling error and comparator voltage offset in the first four phases and suppresses the peak DNL and INL values. A proof-of-concept prototype was fabricated in 0.18-μm 1P6M CMOS technology. At a 0.6-V supply voltage and a 200-kS/s sampling rate, the ADC achieves a signal-to-noise and distortion ratio of 57.97 dB and consumes 1.04 μW, resulting in a figure of merit of 8.03 fJ/conversion-step. The ADC core occupies an active area of only 0.082 mm2.

原文English
文章編號6339066
頁(從 - 到)2783-2795
頁數13
期刊IEEE Journal of Solid-State Circuits
47
發行號11
DOIs
出版狀態Published - 2012 十一月 22

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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