A 1-μW 10-bit 200-kS/s SAR ADC with a bypass window for biomedical applications

Guan Ying Huang, Soon-Jyh Chang, Chun Cheng Liu, Ying Zu Lin

研究成果: Article

87 引文 (Scopus)

摘要

This paper presents an energy efficient successive-approximation-register (SAR) analog-to-digital converter (ADC) for biomedical applications. To reduce energy consumption, a bypass window technique is used to select switching sequences to skip several conversion steps when the signal is within a predefined small window. The power consumptions of the capacitive digital-to-analog converter (DAC), latch comparator, and digital control circuit of the proposed ADC are lower than those of a conventional SAR ADC. The proposed bypass window tolerates the DAC settling error and comparator voltage offset in the first four phases and suppresses the peak DNL and INL values. A proof-of-concept prototype was fabricated in 0.18-μm 1P6M CMOS technology. At a 0.6-V supply voltage and a 200-kS/s sampling rate, the ADC achieves a signal-to-noise and distortion ratio of 57.97 dB and consumes 1.04 μW, resulting in a figure of merit of 8.03 fJ/conversion-step. The ADC core occupies an active area of only 0.082 mm2.

原文English
文章編號6339066
頁(從 - 到)2783-2795
頁數13
期刊IEEE Journal of Solid-State Circuits
47
發行號11
DOIs
出版狀態Published - 2012 十一月 22

指紋

Digital to analog conversion
Comparator circuits
Flip flop circuits
Electric power utilization
Energy utilization
Sampling
Networks (circuits)
Electric potential

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

引用此文

Huang, Guan Ying ; Chang, Soon-Jyh ; Liu, Chun Cheng ; Lin, Ying Zu. / A 1-μW 10-bit 200-kS/s SAR ADC with a bypass window for biomedical applications. 於: IEEE Journal of Solid-State Circuits. 2012 ; 卷 47, 編號 11. 頁 2783-2795.
@article{3cded2b0d6ad4facb795728ad7c06e40,
title = "A 1-μW 10-bit 200-kS/s SAR ADC with a bypass window for biomedical applications",
abstract = "This paper presents an energy efficient successive-approximation-register (SAR) analog-to-digital converter (ADC) for biomedical applications. To reduce energy consumption, a bypass window technique is used to select switching sequences to skip several conversion steps when the signal is within a predefined small window. The power consumptions of the capacitive digital-to-analog converter (DAC), latch comparator, and digital control circuit of the proposed ADC are lower than those of a conventional SAR ADC. The proposed bypass window tolerates the DAC settling error and comparator voltage offset in the first four phases and suppresses the peak DNL and INL values. A proof-of-concept prototype was fabricated in 0.18-μm 1P6M CMOS technology. At a 0.6-V supply voltage and a 200-kS/s sampling rate, the ADC achieves a signal-to-noise and distortion ratio of 57.97 dB and consumes 1.04 μW, resulting in a figure of merit of 8.03 fJ/conversion-step. The ADC core occupies an active area of only 0.082 mm2.",
author = "Huang, {Guan Ying} and Soon-Jyh Chang and Liu, {Chun Cheng} and Lin, {Ying Zu}",
year = "2012",
month = "11",
day = "22",
doi = "10.1109/JSSC.2012.2217635",
language = "English",
volume = "47",
pages = "2783--2795",
journal = "IEEE Journal of Solid-State Circuits",
issn = "0018-9200",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "11",

}

A 1-μW 10-bit 200-kS/s SAR ADC with a bypass window for biomedical applications. / Huang, Guan Ying; Chang, Soon-Jyh; Liu, Chun Cheng; Lin, Ying Zu.

於: IEEE Journal of Solid-State Circuits, 卷 47, 編號 11, 6339066, 22.11.2012, p. 2783-2795.

研究成果: Article

TY - JOUR

T1 - A 1-μW 10-bit 200-kS/s SAR ADC with a bypass window for biomedical applications

AU - Huang, Guan Ying

AU - Chang, Soon-Jyh

AU - Liu, Chun Cheng

AU - Lin, Ying Zu

PY - 2012/11/22

Y1 - 2012/11/22

N2 - This paper presents an energy efficient successive-approximation-register (SAR) analog-to-digital converter (ADC) for biomedical applications. To reduce energy consumption, a bypass window technique is used to select switching sequences to skip several conversion steps when the signal is within a predefined small window. The power consumptions of the capacitive digital-to-analog converter (DAC), latch comparator, and digital control circuit of the proposed ADC are lower than those of a conventional SAR ADC. The proposed bypass window tolerates the DAC settling error and comparator voltage offset in the first four phases and suppresses the peak DNL and INL values. A proof-of-concept prototype was fabricated in 0.18-μm 1P6M CMOS technology. At a 0.6-V supply voltage and a 200-kS/s sampling rate, the ADC achieves a signal-to-noise and distortion ratio of 57.97 dB and consumes 1.04 μW, resulting in a figure of merit of 8.03 fJ/conversion-step. The ADC core occupies an active area of only 0.082 mm2.

AB - This paper presents an energy efficient successive-approximation-register (SAR) analog-to-digital converter (ADC) for biomedical applications. To reduce energy consumption, a bypass window technique is used to select switching sequences to skip several conversion steps when the signal is within a predefined small window. The power consumptions of the capacitive digital-to-analog converter (DAC), latch comparator, and digital control circuit of the proposed ADC are lower than those of a conventional SAR ADC. The proposed bypass window tolerates the DAC settling error and comparator voltage offset in the first four phases and suppresses the peak DNL and INL values. A proof-of-concept prototype was fabricated in 0.18-μm 1P6M CMOS technology. At a 0.6-V supply voltage and a 200-kS/s sampling rate, the ADC achieves a signal-to-noise and distortion ratio of 57.97 dB and consumes 1.04 μW, resulting in a figure of merit of 8.03 fJ/conversion-step. The ADC core occupies an active area of only 0.082 mm2.

UR - http://www.scopus.com/inward/record.url?scp=84869155414&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84869155414&partnerID=8YFLogxK

U2 - 10.1109/JSSC.2012.2217635

DO - 10.1109/JSSC.2012.2217635

M3 - Article

AN - SCOPUS:84869155414

VL - 47

SP - 2783

EP - 2795

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

SN - 0018-9200

IS - 11

M1 - 6339066

ER -