A 1-V 2.4-GHz low-power fractional-N frequency synthesizer with sigma-delta modulator controller

Shuenn-Yuh Lee, Chung Han Cheng, Ming Feng Huang, Shyh Chyang Lee

研究成果: Article

5 引文 (Scopus)

摘要

A 1-V low-power 2.4GHz fractional-N frequency synthesizer with sigma-delta modulator controller for Bluetooth applications is implemented in 0.18 μm CMOS technology. A novel structure dual-modulus divide-by-128/129 prescaler using dynamic D-flip-flop is proposed and the operating clock frequency can reach as high as 2.6 GHz at 1-V supply voltage. Moreover, a third-order feedforward sigmadelta modulator (SDM) is employed as a modulus controller to achieve an appropriate division ratio and suppress the fractional spurs. The simulation results show the synthesizer possesses the tuning range of 2.136 to 2.53 GHz and a phase noise of -126.85 dBc/Hz at 1MHz offset. Moreover, the core area without the SDM and the loop filter is 0.85 mm2, and the total power consumption is 8.94 mW.

原文English
文章編號1465211
頁(從 - 到)2811-2814
頁數4
期刊Proceedings - IEEE International Symposium on Circuits and Systems
DOIs
出版狀態Published - 2005

指紋

Frequency synthesizers
Modulators
Controllers
Flip flop circuits
Bluetooth
Phase noise
Clocks
Electric power utilization
Tuning
Electric potential

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

引用此文

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abstract = "A 1-V low-power 2.4GHz fractional-N frequency synthesizer with sigma-delta modulator controller for Bluetooth applications is implemented in 0.18 μm CMOS technology. A novel structure dual-modulus divide-by-128/129 prescaler using dynamic D-flip-flop is proposed and the operating clock frequency can reach as high as 2.6 GHz at 1-V supply voltage. Moreover, a third-order feedforward sigmadelta modulator (SDM) is employed as a modulus controller to achieve an appropriate division ratio and suppress the fractional spurs. The simulation results show the synthesizer possesses the tuning range of 2.136 to 2.53 GHz and a phase noise of -126.85 dBc/Hz at 1MHz offset. Moreover, the core area without the SDM and the loop filter is 0.85 mm2, and the total power consumption is 8.94 mW.",
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AU - Cheng, Chung Han

AU - Huang, Ming Feng

AU - Lee, Shyh Chyang

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