摘要
A 1-V low-power 2.4GHz fractional-N frequency synthesizer with sigma-delta modulator controller for Bluetooth applications is implemented in 0.18 μm CMOS technology. A novel structure dual-modulus divide-by-128/129 prescaler using dynamic D-flip-flop is proposed and the operating clock frequency can reach as high as 2.6 GHz at 1-V supply voltage. Moreover, a third-order feedforward sigmadelta modulator (SDM) is employed as a modulus controller to achieve an appropriate division ratio and suppress the fractional spurs. The simulation results show the synthesizer possesses the tuning range of 2.136 to 2.53 GHz and a phase noise of -126.85 dBc/Hz at 1MHz offset. Moreover, the core area without the SDM and the loop filter is 0.85 mm2, and the total power consumption is 8.94 mW.
| 原文 | English |
|---|---|
| 文章編號 | 1465211 |
| 頁(從 - 到) | 2811-2814 |
| 頁數 | 4 |
| 期刊 | Proceedings - IEEE International Symposium on Circuits and Systems |
| DOIs | |
| 出版狀態 | Published - 2005 |
| 事件 | IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan 持續時間: 2005 5月 23 → 2005 5月 26 |
All Science Journal Classification (ASJC) codes
- 電氣與電子工程
指紋
深入研究「A 1-V 2.4-GHz low-power fractional-N frequency synthesizer with sigma-delta modulator controller」主題。共同形成了獨特的指紋。引用此
- APA
- Author
- BIBTEX
- Harvard
- Standard
- RIS
- Vancouver