A 1-V, 9-bit, 2.5-M sample/s pipelined ADC with merged switched-opamp and opamp-sharing techniques

Hsin Hung Ou, Bin Da Liu

研究成果: Conference article

3 引文 (Scopus)

摘要

This paper exploits the possibility to merge opamp-sharing technique into switched-opamp configuration. In a switched-opamp based design, the capacitors connected to the opamp output are not switchable, therefore the insertion of opamp-sharing technique demands two output stages within an opamp. A 1-V 9-bit 2.5-MSample/s pipelined analog-to-digital converter is designed to verify the proposed idea. Simulated with TSMC 0.35 μm CMOS 2P4M process models, the results show that differential nonlinearity and integral nonlinearity are 0.5 and 0.65 LSB, respectively. SNDR of pipelined ADC achieves 53.4 dB at 2.5 MHz clock rate. The power consumption is 15 mW at 1 V supply.

原文English
文章編號1465001
頁(從 - 到)1972-1975
頁數4
期刊Proceedings - IEEE International Symposium on Circuits and Systems
DOIs
出版狀態Published - 2005 十二月 1
事件IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan
持續時間: 2005 五月 232005 五月 26

指紋

Operational amplifiers
Digital to analog conversion
Clocks
Electric power utilization
Capacitors

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

引用此文

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