摘要
This paper exploits the possibility to merge opamp-sharing technique into switched-opamp configuration. In a switched-opamp based design, the capacitors connected to the opamp output are not switchable, therefore the insertion of opamp-sharing technique demands two output stages within an opamp. A 1-V 9-bit 2.5-MSample/s pipelined analog-to-digital converter is designed to verify the proposed idea. Simulated with TSMC 0.35 μm CMOS 2P4M process models, the results show that differential nonlinearity and integral nonlinearity are 0.5 and 0.65 LSB, respectively. SNDR of pipelined ADC achieves 53.4 dB at 2.5 MHz clock rate. The power consumption is 15 mW at 1 V supply.
| 原文 | English |
|---|---|
| 文章編號 | 1465001 |
| 頁（從 - 到） | 1972-1975 |
| 頁數 | 4 |
| 期刊 | Proceedings - IEEE International Symposium on Circuits and Systems |
| DOIs | |
| 出版狀態 | Published - 2005 十二月 1 |
| 事件 | IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan 持續時間: 2005 五月 23 → 2005 五月 26 |
指紋
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
引用此文
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A 1-V, 9-bit, 2.5-M sample/s pipelined ADC with merged switched-opamp and opamp-sharing techniques. / Ou, Hsin Hung; Liu, Bin Da.
於: Proceedings - IEEE International Symposium on Circuits and Systems, 01.12.2005, p. 1972-1975.研究成果: Conference article
TY - JOUR
T1 - A 1-V, 9-bit, 2.5-M sample/s pipelined ADC with merged switched-opamp and opamp-sharing techniques
AU - Ou, Hsin Hung
AU - Liu, Bin Da
PY - 2005/12/1
Y1 - 2005/12/1
N2 - This paper exploits the possibility to merge opamp-sharing technique into switched-opamp configuration. In a switched-opamp based design, the capacitors connected to the opamp output are not switchable, therefore the insertion of opamp-sharing technique demands two output stages within an opamp. A 1-V 9-bit 2.5-MSample/s pipelined analog-to-digital converter is designed to verify the proposed idea. Simulated with TSMC 0.35 μm CMOS 2P4M process models, the results show that differential nonlinearity and integral nonlinearity are 0.5 and 0.65 LSB, respectively. SNDR of pipelined ADC achieves 53.4 dB at 2.5 MHz clock rate. The power consumption is 15 mW at 1 V supply.
AB - This paper exploits the possibility to merge opamp-sharing technique into switched-opamp configuration. In a switched-opamp based design, the capacitors connected to the opamp output are not switchable, therefore the insertion of opamp-sharing technique demands two output stages within an opamp. A 1-V 9-bit 2.5-MSample/s pipelined analog-to-digital converter is designed to verify the proposed idea. Simulated with TSMC 0.35 μm CMOS 2P4M process models, the results show that differential nonlinearity and integral nonlinearity are 0.5 and 0.65 LSB, respectively. SNDR of pipelined ADC achieves 53.4 dB at 2.5 MHz clock rate. The power consumption is 15 mW at 1 V supply.
UR - http://www.scopus.com/inward/record.url?scp=67649122211&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=67649122211&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2005.1465001
DO - 10.1109/ISCAS.2005.1465001
M3 - Conference article
AN - SCOPUS:67649122211
SP - 1972
EP - 1975
JO - Proceedings - IEEE International Symposium on Circuits and Systems
JF - Proceedings - IEEE International Symposium on Circuits and Systems
SN - 0271-4310
M1 - 1465001
ER -