A 1 V CMOS analog comparator using auto-zero and complementary differential-input technique

Yu Cherng Hung, Bin Da Liu

研究成果: Conference contribution

4 引文 (Scopus)

摘要

A CMOS comparator operating over a 1 V to 5 V supply range is presented. No special low-voltage technology is used for fabrication. An experimental chip was fabricated using a 0.5 μm 5 V CMOS double-poly double-metal technology. The chip area of the comparator was 230×160 μm2. Measured results at 1 V supply voltage show a comparator response time of less than 4 μs for 10 mV precision. Static power consumptions at 1 V supply voltage including input/output pads for comparator is 1 μW.

原文English
主出版物標題2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings
發行者Institute of Electrical and Electronics Engineers Inc.
頁面181-184
頁數4
ISBN(電子)0780373634, 9780780373631
DOIs
出版狀態Published - 2002 一月 1
事件3rd IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Taipei, Taiwan
持續時間: 2002 八月 62002 八月 8

出版系列

名字2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings

Other

Other3rd IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002
國家Taiwan
城市Taipei
期間02-08-0602-08-08

指紋

Electric potential
Electric power utilization
Fabrication
Metals

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

引用此文

Hung, Y. C., & Liu, B. D. (2002). A 1 V CMOS analog comparator using auto-zero and complementary differential-input technique. 於 2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings (頁 181-184). [1031562] (2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APASIC.2002.1031562
Hung, Yu Cherng ; Liu, Bin Da. / A 1 V CMOS analog comparator using auto-zero and complementary differential-input technique. 2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2002. 頁 181-184 (2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings).
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Hung, YC & Liu, BD 2002, A 1 V CMOS analog comparator using auto-zero and complementary differential-input technique. 於 2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings., 1031562, 2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings, Institute of Electrical and Electronics Engineers Inc., 頁 181-184, 3rd IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002, Taipei, Taiwan, 02-08-06. https://doi.org/10.1109/APASIC.2002.1031562

A 1 V CMOS analog comparator using auto-zero and complementary differential-input technique. / Hung, Yu Cherng; Liu, Bin Da.

2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2002. p. 181-184 1031562 (2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings).

研究成果: Conference contribution

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N2 - A CMOS comparator operating over a 1 V to 5 V supply range is presented. No special low-voltage technology is used for fabrication. An experimental chip was fabricated using a 0.5 μm 5 V CMOS double-poly double-metal technology. The chip area of the comparator was 230×160 μm2. Measured results at 1 V supply voltage show a comparator response time of less than 4 μs for 10 mV precision. Static power consumptions at 1 V supply voltage including input/output pads for comparator is 1 μW.

AB - A CMOS comparator operating over a 1 V to 5 V supply range is presented. No special low-voltage technology is used for fabrication. An experimental chip was fabricated using a 0.5 μm 5 V CMOS double-poly double-metal technology. The chip area of the comparator was 230×160 μm2. Measured results at 1 V supply voltage show a comparator response time of less than 4 μs for 10 mV precision. Static power consumptions at 1 V supply voltage including input/output pads for comparator is 1 μW.

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Hung YC, Liu BD. A 1 V CMOS analog comparator using auto-zero and complementary differential-input technique. 於 2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2002. p. 181-184. 1031562. (2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings). https://doi.org/10.1109/APASIC.2002.1031562