A 10-bit 12-MS/s successive approximation ADC with 1.2-pF input capacitance

Guan Ying Huang, Chun Cheng Liu, Ying Zu Lin, Soon Jyh Chang

研究成果: Conference contribution

20 引文 斯高帕斯(Scopus)

摘要

This paper reports a successive-approximation analog-to-digital converter (ADC) with low input capacitance. The 10-bit prototype is fabricated in a 0.13-μm CMOS process. Compared to conventional successive approximation ADCs, the proposed ADC reduces the input capacitance to 1.2 pF for 10-bit resolution. At 12 MS/s and 1.2-V supply, this ADC consumes 0.32 mW and achieves an SNDR of 50.89 dB, resulting in an FOM of 95 fJ/Conversion-step.

原文English
主出版物標題Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009
頁面157-160
頁數4
DOIs
出版狀態Published - 2009 十二月 1
事件2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009 - Taipei, Taiwan
持續時間: 2009 十一月 162009 十一月 18

出版系列

名字Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009

Other

Other2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009
國家/地區Taiwan
城市Taipei
期間09-11-1609-11-18

All Science Journal Classification (ASJC) codes

  • 硬體和架構
  • 電氣與電子工程

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