A 10-bit 350-MSample/s Nyquist CMOS digital-to-analog converter (DAC) is proposed in this paper. Segmented current steering architecture that comprises 6MSB's unary cells and 4LSB's binary-weighted cells is applied in this design. Cascoded switch structure is adopted in the current cell which increases the performance of the segmented DAC. The simulation results show that integral nonlinearity is better than +0.15 LSB and differential nonlinearity is between +0.1 LSB. SNDR better than 60dB is simulated in the interval from dc to the Nyquist frequency. The power consumption of this DAC with a single 2.5V supply is 36mW for a near-Nyquist fundamental signal at a 350-MHz update rate.
|出版狀態||Published - 2004 十二月 1|
|事件||2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology - Tainan, Taiwan|
持續時間: 2004 十二月 6 → 2004 十二月 9
|Other||2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology|
|期間||04-12-06 → 04-12-09|
All Science Journal Classification (ASJC) codes