A 10-bit 350-MSample/s Nyquist CMOS D/A converter

Jeng Dau Chang, Hsin Hung Ou, Bin-Da Liu

研究成果: Paper

摘要

A 10-bit 350-MSample/s Nyquist CMOS digital-to-analog converter (DAC) is proposed in this paper. Segmented current steering architecture that comprises 6MSB's unary cells and 4LSB's binary-weighted cells is applied in this design. Cascoded switch structure is adopted in the current cell which increases the performance of the segmented DAC. The simulation results show that integral nonlinearity is better than +0.15 LSB and differential nonlinearity is between +0.1 LSB. SNDR better than 60dB is simulated in the interval from dc to the Nyquist frequency. The power consumption of this DAC with a single 2.5V supply is 36mW for a near-Nyquist fundamental signal at a 350-MHz update rate.

原文English
頁面621-624
頁數4
出版狀態Published - 2004 十二月 1
事件2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology - Tainan, Taiwan
持續時間: 2004 十二月 62004 十二月 9

Other

Other2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology
國家Taiwan
城市Tainan
期間04-12-0604-12-09

指紋

Digital to analog conversion
Electric power utilization
Switches

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

引用此文

Chang, J. D., Ou, H. H., & Liu, B-D. (2004). A 10-bit 350-MSample/s Nyquist CMOS D/A converter. 621-624. 論文發表於 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology, Tainan, Taiwan.
Chang, Jeng Dau ; Ou, Hsin Hung ; Liu, Bin-Da. / A 10-bit 350-MSample/s Nyquist CMOS D/A converter. 論文發表於 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology, Tainan, Taiwan.4 p.
@conference{eb5494fa433b4b9b851466b96b78b066,
title = "A 10-bit 350-MSample/s Nyquist CMOS D/A converter",
abstract = "A 10-bit 350-MSample/s Nyquist CMOS digital-to-analog converter (DAC) is proposed in this paper. Segmented current steering architecture that comprises 6MSB's unary cells and 4LSB's binary-weighted cells is applied in this design. Cascoded switch structure is adopted in the current cell which increases the performance of the segmented DAC. The simulation results show that integral nonlinearity is better than +0.15 LSB and differential nonlinearity is between +0.1 LSB. SNDR better than 60dB is simulated in the interval from dc to the Nyquist frequency. The power consumption of this DAC with a single 2.5V supply is 36mW for a near-Nyquist fundamental signal at a 350-MHz update rate.",
author = "Chang, {Jeng Dau} and Ou, {Hsin Hung} and Bin-Da Liu",
year = "2004",
month = "12",
day = "1",
language = "English",
pages = "621--624",
note = "2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology ; Conference date: 06-12-2004 Through 09-12-2004",

}

Chang, JD, Ou, HH & Liu, B-D 2004, 'A 10-bit 350-MSample/s Nyquist CMOS D/A converter', 論文發表於 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology, Tainan, Taiwan, 04-12-06 - 04-12-09 頁 621-624.

A 10-bit 350-MSample/s Nyquist CMOS D/A converter. / Chang, Jeng Dau; Ou, Hsin Hung; Liu, Bin-Da.

2004. 621-624 論文發表於 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology, Tainan, Taiwan.

研究成果: Paper

TY - CONF

T1 - A 10-bit 350-MSample/s Nyquist CMOS D/A converter

AU - Chang, Jeng Dau

AU - Ou, Hsin Hung

AU - Liu, Bin-Da

PY - 2004/12/1

Y1 - 2004/12/1

N2 - A 10-bit 350-MSample/s Nyquist CMOS digital-to-analog converter (DAC) is proposed in this paper. Segmented current steering architecture that comprises 6MSB's unary cells and 4LSB's binary-weighted cells is applied in this design. Cascoded switch structure is adopted in the current cell which increases the performance of the segmented DAC. The simulation results show that integral nonlinearity is better than +0.15 LSB and differential nonlinearity is between +0.1 LSB. SNDR better than 60dB is simulated in the interval from dc to the Nyquist frequency. The power consumption of this DAC with a single 2.5V supply is 36mW for a near-Nyquist fundamental signal at a 350-MHz update rate.

AB - A 10-bit 350-MSample/s Nyquist CMOS digital-to-analog converter (DAC) is proposed in this paper. Segmented current steering architecture that comprises 6MSB's unary cells and 4LSB's binary-weighted cells is applied in this design. Cascoded switch structure is adopted in the current cell which increases the performance of the segmented DAC. The simulation results show that integral nonlinearity is better than +0.15 LSB and differential nonlinearity is between +0.1 LSB. SNDR better than 60dB is simulated in the interval from dc to the Nyquist frequency. The power consumption of this DAC with a single 2.5V supply is 36mW for a near-Nyquist fundamental signal at a 350-MHz update rate.

UR - http://www.scopus.com/inward/record.url?scp=13444311899&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=13444311899&partnerID=8YFLogxK

M3 - Paper

AN - SCOPUS:13444311899

SP - 621

EP - 624

ER -

Chang JD, Ou HH, Liu B-D. A 10-bit 350-MSample/s Nyquist CMOS D/A converter. 2004. 論文發表於 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology, Tainan, Taiwan.