A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure

Chun Cheng Liu, Soon Jyh Chang, Guan Ying Huang, Ying Zu Lin

研究成果: Article同行評審

738 引文 斯高帕斯(Scopus)

摘要

This paper presents a low-power 10-bit 50-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) that uses a monotonic capacitor switching procedure. Compared to converters that use the conventional procedure, the average switching energy and total capacitance are reduced by about 81% and 50%, respectively. In the switching procedure, the input common-mode voltage gradually converges to ground. An improved comparator diminishes the signal-dependent offset caused by the input common-mode voltage variation. The prototype was fabricated using 0.13- μm 1P8M CMOS technology. At a 1.2-V supply and 50 MS/s, the ADC achieves an SNDR of 57.0 dB and consumes 0.826 mW, resulting in a figure of merit (FOM) of 29 fJ/conversion-step. The ADC core occupies an active area of only &195 × 265 μm2.

原文English
文章編號5437496
頁(從 - 到)731-740
頁數10
期刊IEEE Journal of Solid-State Circuits
45
發行號4
DOIs
出版狀態Published - 2010 四月 1

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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