TY - JOUR
T1 - A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure
AU - Liu, Chun Cheng
AU - Chang, Soon Jyh
AU - Huang, Guan Ying
AU - Lin, Ying Zu
N1 - Funding Information:
Manuscript received August 24, 2009; revised January 15, 2010. Current version published March 24, 2010. This paper was approved by Guest Editor Ajith Amerasekera. This work was supported in part by the grant of NSC-98-2221-E-006-156-MY3 and NSC 98-2218-E-006-003 from National Science Council (NSC) and Himax Technologies Inc., Taiwan.
PY - 2010/4
Y1 - 2010/4
N2 - This paper presents a low-power 10-bit 50-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) that uses a monotonic capacitor switching procedure. Compared to converters that use the conventional procedure, the average switching energy and total capacitance are reduced by about 81% and 50%, respectively. In the switching procedure, the input common-mode voltage gradually converges to ground. An improved comparator diminishes the signal-dependent offset caused by the input common-mode voltage variation. The prototype was fabricated using 0.13- μm 1P8M CMOS technology. At a 1.2-V supply and 50 MS/s, the ADC achieves an SNDR of 57.0 dB and consumes 0.826 mW, resulting in a figure of merit (FOM) of 29 fJ/conversion-step. The ADC core occupies an active area of only &195 × 265 μm2.
AB - This paper presents a low-power 10-bit 50-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) that uses a monotonic capacitor switching procedure. Compared to converters that use the conventional procedure, the average switching energy and total capacitance are reduced by about 81% and 50%, respectively. In the switching procedure, the input common-mode voltage gradually converges to ground. An improved comparator diminishes the signal-dependent offset caused by the input common-mode voltage variation. The prototype was fabricated using 0.13- μm 1P8M CMOS technology. At a 1.2-V supply and 50 MS/s, the ADC achieves an SNDR of 57.0 dB and consumes 0.826 mW, resulting in a figure of merit (FOM) of 29 fJ/conversion-step. The ADC core occupies an active area of only &195 × 265 μm2.
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U2 - 10.1109/JSSC.2010.2042254
DO - 10.1109/JSSC.2010.2042254
M3 - Article
AN - SCOPUS:77950287759
SN - 0018-9200
VL - 45
SP - 731
EP - 740
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
IS - 4
M1 - 5437496
ER -