A 10-bit 60-MS/s low-power pipelined ADC with split-capacitor CDS technique

Jin Fu Lin, Soon Jyh Chang, Chun Cheng Liu, Chih Hao Huang

研究成果: Article同行評審

24 引文 斯高帕斯(Scopus)

摘要

In this brief, a split-capacitor correlated double sampling (SC-CDS) technique is proposed to improve the performance of CDS. Using the proposed technique, low-gain operational amplifiers (op-amps) can be employed to implement a low-power pipelined analog-to-digital converter (ADC). A power-efficient class-AB pseudodifferential op-amp and its corresponding integrator-based common-mode stabilization (IB-CMS) method are developed to further reduce the power consumption of the ADC. The proposed pipelined ADC fabricated in a pure digital 0.18-μ 1P5M CMOS process consumes 18 mW at 60 MS/s from a 1.8-V power supply. The active die area is 0.84 mm2.

原文English
文章編號5431013
頁(從 - 到)163-167
頁數5
期刊IEEE Transactions on Circuits and Systems II: Express Briefs
57
發行號3
DOIs
出版狀態Published - 2010 三月 1

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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