A 10-bit segmented digital-to-time converter with 10-ps-level resolution and offset calibration circuits

Keng Hong Chu, Tse An Chen, Chia Ling Wei

研究成果: Conference contribution

2 引文 斯高帕斯(Scopus)

摘要

A 10-bit segmented digital-to-time converter (DTC) with offset calibration is proposed. The segmented architecture (2-bit binary code + 8-bit thermometer code) is adopted in the proposed DTC to reduce the impact of process variation on linearity. Moreover, the relative time generation is used for getting high resolution, and the offset calibration circuit is also implemented to calibrate the offset error inherent in the relative time generation. The proposed DTC was fabricated using the TSMC 0.18μm 1P6M mixed-signal process. The resolution is designed to be in the order of 10ps, and the total output timing range is in the order of 10 ns. The core area is 0.7mm2.

原文English
主出版物標題2016 5th International Symposium on Next-Generation Electronics, ISNE 2016
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781509024391
DOIs
出版狀態Published - 2016 八月 12
事件5th International Symposium on Next-Generation Electronics, ISNE 2016 - Hsinchu, Taiwan
持續時間: 2016 五月 42016 五月 6

出版系列

名字2016 5th International Symposium on Next-Generation Electronics, ISNE 2016

Other

Other5th International Symposium on Next-Generation Electronics, ISNE 2016
國家/地區Taiwan
城市Hsinchu
期間16-05-0416-05-06

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程
  • 電子、光磁材料

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